Search

Pierre E Elisca

Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715
Total Applications
2631
Issued Applications
2140
Pending Applications
221
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9504231 [patent_doc_number] => 08742549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Shallow trench isolation structure' [patent_app_type] => utility [patent_app_number] => 13/239375 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2237 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/239375
Shallow trench isolation structure Sep 20, 2011 Issued
Array ( [id] => 7711281 [patent_doc_number] => 20120003829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/228397 [patent_app_country] => US [patent_app_date] => 2011-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3688 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228397 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228397
Metal-insulator-metal capacitor alloying process Sep 7, 2011 Issued
Array ( [id] => 7807634 [patent_doc_number] => 20120058588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'DEVICE AND METHOD FOR SIMULTANEOUSLY MICROSTRUCTURING AND DOPING SEMICONDUCTOR SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 13/223379 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2751 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20120058588.pdf [firstpage_image] =>[orig_patent_app_number] => 13223379 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/223379
DEVICE AND METHOD FOR SIMULTANEOUSLY MICROSTRUCTURING AND DOPING SEMICONDUCTOR SUBSTRATES Aug 31, 2011 Abandoned
Array ( [id] => 8684524 [patent_doc_number] => 20130052808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'METHOD OF DEPOSITING HIGHLY CONFORMAL AMORPHOUS CARBON FILMS OVER RAISED FEATURES' [patent_app_type] => utility [patent_app_number] => 13/217813 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4476 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217813 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217813
Method of depositing highly conformal amorphous carbon films over raised features Aug 24, 2011 Issued
Array ( [id] => 8210150 [patent_doc_number] => 20120129284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY PIXEL ARRAY' [patent_app_type] => utility [patent_app_number] => 13/217633 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2939 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20120129284.pdf [firstpage_image] =>[orig_patent_app_number] => 13217633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217633
METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY PIXEL ARRAY Aug 24, 2011 Abandoned
Array ( [id] => 8680921 [patent_doc_number] => 20130049205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps' [patent_app_type] => utility [patent_app_number] => 13/218265 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5996 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13218265 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/218265
Chip with encapsulated sides and exposed surface Aug 24, 2011 Issued
Array ( [id] => 9059725 [patent_doc_number] => 08546159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Phosphor film, method of forming the same, and method of coating phosphor layer on LED chips' [patent_app_type] => utility [patent_app_number] => 13/217828 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 38 [patent_no_of_words] => 5986 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217828
Phosphor film, method of forming the same, and method of coating phosphor layer on LED chips Aug 24, 2011 Issued
Array ( [id] => 9140234 [patent_doc_number] => 08580694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Method of patterning hard mask layer for defining deep trench' [patent_app_type] => utility [patent_app_number] => 13/218281 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1620 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13218281 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/218281
Method of patterning hard mask layer for defining deep trench Aug 24, 2011 Issued
Array ( [id] => 8684475 [patent_doc_number] => 20130052759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'VERTICAL SOLID-STATE TRANSDUCERS HAVING BACKSIDE TERMINALS AND ASSOCIATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/218289 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6235 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13218289 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/218289
Vertical solid-state transducers having backside terminals and associated systems and methods Aug 24, 2011 Issued
Array ( [id] => 10158477 [patent_doc_number] => 09190261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Layer alignment in FinFET fabrication' [patent_app_type] => utility [patent_app_number] => 13/217702 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 4551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217702 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217702
Layer alignment in FinFET fabrication Aug 24, 2011 Issued
Array ( [id] => 8240454 [patent_doc_number] => 20120149195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 13/217439 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217439 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217439
METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE Aug 24, 2011 Abandoned
Array ( [id] => 8684496 [patent_doc_number] => 20130052781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'Method of Forming Non-planar FET' [patent_app_type] => utility [patent_app_number] => 13/218438 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2081 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13218438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/218438
Method of forming non-planar FET Aug 24, 2011 Issued
Array ( [id] => 8920873 [patent_doc_number] => 08486806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Method for machining wafers by cutting partway through a peripheral surplus region to form break starting points' [patent_app_type] => utility [patent_app_number] => 13/217468 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3123 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217468 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217468
Method for machining wafers by cutting partway through a peripheral surplus region to form break starting points Aug 24, 2011 Issued
Array ( [id] => 7791085 [patent_doc_number] => 20120052641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'Methods of Manufacturing MOS Transistors' [patent_app_type] => utility [patent_app_number] => 13/217871 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9675 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20120052641.pdf [firstpage_image] =>[orig_patent_app_number] => 13217871 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217871
Methods of Manufacturing MOS Transistors Aug 24, 2011 Abandoned
Array ( [id] => 7648681 [patent_doc_number] => 20110297950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'CRYSTALLINE SEMICONDUCTOR FILM MANUFACTURING METHOD, SUBSTRATE COATED WITH CRYSTALLINE SEMICONDUCTOR FILM, AND THIN-FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/212465 [patent_app_country] => US [patent_app_date] => 2011-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20110297950.pdf [firstpage_image] =>[orig_patent_app_number] => 13212465 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/212465
CRYSTALLINE SEMICONDUCTOR FILM MANUFACTURING METHOD, SUBSTRATE COATED WITH CRYSTALLINE SEMICONDUCTOR FILM, AND THIN-FILM TRANSISTOR Aug 17, 2011 Abandoned
Array ( [id] => 7651433 [patent_doc_number] => 20110300702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/210983 [patent_app_country] => US [patent_app_date] => 2011-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3705 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20110300702.pdf [firstpage_image] =>[orig_patent_app_number] => 13210983 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/210983
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Aug 15, 2011 Abandoned
Array ( [id] => 9691652 [patent_doc_number] => 08822246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Method for manufacturing a light-emitting element including a protective film for a charge injection layer' [patent_app_type] => utility [patent_app_number] => 13/205765 [patent_app_country] => US [patent_app_date] => 2011-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 10944 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13205765 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/205765
Method for manufacturing a light-emitting element including a protective film for a charge injection layer Aug 8, 2011 Issued
Array ( [id] => 7767166 [patent_doc_number] => 20120034714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'WAFER-LEVEL LIGHT EMITTING DIODE STRUCTURE, LIGHT EMITTING DIODE CHIP, AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/197677 [patent_app_country] => US [patent_app_date] => 2011-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 7053 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20120034714.pdf [firstpage_image] =>[orig_patent_app_number] => 13197677 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/197677
Wafer-level light emitting diode structure, light emitting diode chip, and method for forming the same Aug 2, 2011 Issued
Array ( [id] => 8764996 [patent_doc_number] => 20130093033 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2013-04-18 [patent_title] => 'THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS' [patent_app_type] => utility [patent_app_number] => 13/195583 [patent_app_country] => US [patent_app_date] => 2011-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5205 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13195583 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/195583
THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS Jul 31, 2011 Abandoned
Array ( [id] => 8764996 [patent_doc_number] => 20130093033 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2013-04-18 [patent_title] => 'THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS' [patent_app_type] => utility [patent_app_number] => 13/195583 [patent_app_country] => US [patent_app_date] => 2011-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5205 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13195583 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/195583
THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS Jul 31, 2011 Abandoned
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