Pierre E Elisca

Array ( [id] => 7567541 [patent_doc_number] => 20110287604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING DIRECT BONDING OF SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 13/195605 [patent_app_country] => US [patent_app_date] => 2011-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5225 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20110287604.pdf [firstpage_image] =>[orig_patent_app_number] => 13195605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9594515 [patent_doc_number] => 20140191192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'SEMICONDUCTOR LIGHT-EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/235705 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5373 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14235705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10851490 [patent_doc_number] => 08878173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Semiconductor device including oxide semiconductor and metal oxide' [patent_app_type] => utility [patent_app_number] => 13/171029 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 45 [patent_no_of_words] => 20956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7805335 [patent_doc_number] => 20120056287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'DISPOSITIF DE DETECTION DE RAYONNEMENT ET PROCEDE DE FABRICATION' [patent_app_type] => utility [patent_app_number] => 13/170819 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7729 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20120056287.pdf [firstpage_image] =>[orig_patent_app_number] => 13170819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8582920 [patent_doc_number] => 20130001741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/171228 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8582922 [patent_doc_number] => 20130001743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'METAL INSULATOR METAL STRUCTURE WITH REMOTE OXYGEN SCAVENGING' [patent_app_type] => utility [patent_app_number] => 13/171044 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4506 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8582874 [patent_doc_number] => 20130001695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS)' [patent_app_type] => utility [patent_app_number] => 13/171037 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4975 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8582826 [patent_doc_number] => 20130001647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'INTEGRATION OF VERTICAL BJT OR HBT INTO SOI TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 13/170473 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2230 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8582873 [patent_doc_number] => 20130001694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE' [patent_app_type] => utility [patent_app_number] => 13/170965 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6100 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7706658 [patent_doc_number] => 20120001318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/170475 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10144 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9140134 [patent_doc_number] => 08580591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Method of manufacturing vertical pin diodes' [patent_app_type] => utility [patent_app_number] => 13/171053 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6009 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9590030 [patent_doc_number] => 08779573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Semiconductor package having a silicon reinforcing member embedded in resin' [patent_app_type] => utility [patent_app_number] => 13/170319 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 3368 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8166023 [patent_doc_number] => 20120104383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING ZINC OXIDE THIN FILM AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/169424 [patent_app_country] => US [patent_app_date] => 2011-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3324 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104383.pdf [firstpage_image] =>[orig_patent_app_number] => 13169424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9524765 [patent_doc_number] => 08749042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Process for making a semiconductor system' [patent_app_type] => utility [patent_app_number] => 13/166996 [patent_app_country] => US [patent_app_date] => 2011-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4144 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7479970 [patent_doc_number] => 20110248324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'DUAL-GATE NON-VOLATILE FERROELECTRIC MEMORY' [patent_app_type] => utility [patent_app_number] => 13/166076 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8624 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248324.pdf [firstpage_image] =>[orig_patent_app_number] => 13166076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7486096 [patent_doc_number] => 20110250721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'STACKED AND SHIELDED PACKAGES WITH INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 13/165371 [patent_app_country] => US [patent_app_date] => 2011-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10096 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20110250721.pdf [firstpage_image] =>[orig_patent_app_number] => 13165371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7479812 [patent_doc_number] => 20110248265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Backside texturing by cusps to improve IR response of silicon solar cells and photodetectors' [patent_app_type] => utility [patent_app_number] => 13/134749 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7612 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248265.pdf [firstpage_image] =>[orig_patent_app_number] => 13134749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5936891 [patent_doc_number] => 20110212550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'METHODS FOR DETECTING METAL PRECIPITATES IN A SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 13/105392 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6992 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20110212550.pdf [firstpage_image] =>[orig_patent_app_number] => 13105392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5936876 [patent_doc_number] => 20110212547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'METHODS FOR MONITORING THE AMOUNT OF METAL CONTAMINATION IMPARTED INTO WAFERS DURING A SEMICONDUCTOR PROCESS' [patent_app_type] => utility [patent_app_number] => 13/105381 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6987 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20110212547.pdf [firstpage_image] =>[orig_patent_app_number] => 13105381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7486175 [patent_doc_number] => 20110250743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'METHOD FOR PRODUCING A TRANSISTOR GATE WITH SUB-PHOTOLITHOGRAPHIC DIMENSIONS' [patent_app_type] => utility [patent_app_number] => 13/084820 [patent_app_country] => US [patent_app_date] => 2011-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2485 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20110250743.pdf [firstpage_image] =>[orig_patent_app_number] => 13084820 [rel_patent_id] =>[rel_patent_doc_number] =>)