Pierre E Elisca

Array ( [id] => 6235516 [patent_doc_number] => 20100267220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Methods Of Depositing Antimony-Comprising Phase Change Material Onto A Substrate And Methods Of Forming Phase Change Memory Circuitry' [patent_app_type] => utility [patent_app_number] => 12/424387 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3326 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20100267220.pdf [firstpage_image] =>[orig_patent_app_number] => 12424387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6235491 [patent_doc_number] => 20100267195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Methods Of Forming Phase Change Materials And Methods Of Forming Phase Change Memory Circuitry' [patent_app_type] => utility [patent_app_number] => 12/424404 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6523 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20100267195.pdf [firstpage_image] =>[orig_patent_app_number] => 12424404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7774048 [patent_doc_number] => 08119545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Forming a silicon nitride film by plasma CVD' [patent_app_type] => utility [patent_app_number] => 12/935138 [patent_app_country] => US [patent_app_date] => 2009-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 14969 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/119/08119545.pdf [firstpage_image] =>[orig_patent_app_number] => 12935138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6126834 [patent_doc_number] => 20110086485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'METHOD FOR MANUFACTURING A MOS SEMICONDUCTOR MEMORY DEVICE, AND PLASMA CVD DEVICE' [patent_app_type] => utility [patent_app_number] => 12/935792 [patent_app_country] => US [patent_app_date] => 2009-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13854 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20110086485.pdf [firstpage_image] =>[orig_patent_app_number] => 12935792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6202475 [patent_doc_number] => 20110065261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'DICING METHOD' [patent_app_type] => utility [patent_app_number] => 12/992616 [patent_app_country] => US [patent_app_date] => 2009-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5405 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20110065261.pdf [firstpage_image] =>[orig_patent_app_number] => 12992616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6494986 [patent_doc_number] => 20100200977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Layered chip package and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 12/320884 [patent_app_country] => US [patent_app_date] => 2009-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 29372 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200977.pdf [firstpage_image] =>[orig_patent_app_number] => 12320884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7570949 [patent_doc_number] => 20110266605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Memristive Transistor Memory' [patent_app_type] => utility [patent_app_number] => 13/142581 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3830 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266605.pdf [firstpage_image] =>[orig_patent_app_number] => 13142581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4644307 [patent_doc_number] => 08021912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Method of fabricating an image sensor having an annealing layer' [patent_app_type] => utility [patent_app_number] => 12/320543 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4511 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/021/08021912.pdf [firstpage_image] =>[orig_patent_app_number] => 12320543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5278666 [patent_doc_number] => 20090130798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Process for Making a Semiconductor System' [patent_app_type] => utility [patent_app_number] => 12/361513 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4104 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20090130798.pdf [firstpage_image] =>[orig_patent_app_number] => 12361513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6143640 [patent_doc_number] => 20110129983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'METHOD FOR FABRICATING A DUAL-ORIENTATION GROUP-IV SEMICONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/864649 [patent_app_country] => US [patent_app_date] => 2009-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4678 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20110129983.pdf [firstpage_image] =>[orig_patent_app_number] => 12864649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 92002 [patent_doc_number] => 07732313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'FUSI integration method using SOG as a sacrificial planarization layer' [patent_app_type] => utility [patent_app_number] => 12/348660 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 5206 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732313.pdf [firstpage_image] =>[orig_patent_app_number] => 12348660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5330732 [patent_doc_number] => 20090111209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'METHOD FOR PATTERNING MO LAYER IN A PHOTOVOLTAIC DEVICE COMPRISING CIGS MATERIAL USING AN ETCH PROCESS' [patent_app_type] => utility [patent_app_number] => 12/346750 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3865 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20090111209.pdf [firstpage_image] =>[orig_patent_app_number] => 12346750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6410489 [patent_doc_number] => 20100140780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'Semiconductor Device and Method of Forming an IPD Beneath a Semiconductor Die with Direct Connection to External Devices' [patent_app_type] => utility [patent_app_number] => 12/332253 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7610 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20100140780.pdf [firstpage_image] =>[orig_patent_app_number] => 12332253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5439319 [patent_doc_number] => 20090090958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Semiconductor Constructions' [patent_app_type] => utility [patent_app_number] => 12/331059 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3909 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20090090958.pdf [firstpage_image] =>[orig_patent_app_number] => 12331059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5542825 [patent_doc_number] => 20090152702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Coupling wire to semiconductor region' [patent_app_type] => utility [patent_app_number] => 12/380974 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10425 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20090152702.pdf [firstpage_image] =>[orig_patent_app_number] => 12380974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6410568 [patent_doc_number] => 20100140788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING' [patent_app_type] => utility [patent_app_number] => 12/330044 [patent_app_country] => US [patent_app_date] => 2008-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6436 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20100140788.pdf [firstpage_image] =>[orig_patent_app_number] => 12330044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4599390 [patent_doc_number] => 07977161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Method of manufacturing a semiconductor package using a carrier' [patent_app_type] => utility [patent_app_number] => 12/292343 [patent_app_country] => US [patent_app_date] => 2008-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 84 [patent_no_of_words] => 4867 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/977/07977161.pdf [firstpage_image] =>[orig_patent_app_number] => 12292343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5407453 [patent_doc_number] => 20090121351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Process for forming a bump structure and bump structure' [patent_app_type] => utility [patent_app_number] => 12/290873 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11570 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121351.pdf [firstpage_image] =>[orig_patent_app_number] => 12290873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5410178 [patent_doc_number] => 20090124077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Method for forming poly-silicon film' [patent_app_type] => utility [patent_app_number] => 12/285574 [patent_app_country] => US [patent_app_date] => 2008-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6123 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20090124077.pdf [firstpage_image] =>[orig_patent_app_number] => 12285574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5521561 [patent_doc_number] => 20090029542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'METHODS AND SYSTEMS FOR LASER ASSISTED WIREBONDING' [patent_app_type] => utility [patent_app_number] => 12/240372 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3118 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20090029542.pdf [firstpage_image] =>[orig_patent_app_number] => 12240372 [rel_patent_id] =>[rel_patent_doc_number] =>)