Search

Pierre E Elisca

Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715
Total Applications
2631
Issued Applications
2140
Pending Applications
221
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5441455 [patent_doc_number] => 20090093094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Selective Formation of Silicon Carbon Epitaxial Layer' [patent_app_type] => utility [patent_app_number] => 11/867933 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20090093094.pdf [firstpage_image] =>[orig_patent_app_number] => 11867933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867933
Selective formation of silicon carbon epitaxial layer Oct 4, 2007 Issued
Array ( [id] => 4682415 [patent_doc_number] => 20080248641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/905074 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2707 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20080248641.pdf [firstpage_image] =>[orig_patent_app_number] => 11905074 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905074
Method of manufacturing semiconductor device Sep 26, 2007 Abandoned
Array ( [id] => 4745712 [patent_doc_number] => 20080090314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 11/859243 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12183 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20080090314.pdf [firstpage_image] =>[orig_patent_app_number] => 11859243 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/859243
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME Sep 20, 2007 Abandoned
Array ( [id] => 4938879 [patent_doc_number] => 20080076198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Method of manufacturing light emitting diode package and white light source module' [patent_app_type] => utility [patent_app_number] => 11/902233 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3118 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20080076198.pdf [firstpage_image] =>[orig_patent_app_number] => 11902233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902233
Method of manufacturing light emitting diode package and white light source module Sep 19, 2007 Abandoned
Array ( [id] => 4692813 [patent_doc_number] => 20080085584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'OXIDATION/HEAT TREATMENT METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 11/857824 [patent_app_country] => US [patent_app_date] => 2007-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085584.pdf [firstpage_image] =>[orig_patent_app_number] => 11857824 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/857824
OXIDATION/HEAT TREATMENT METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES Sep 18, 2007 Abandoned
Array ( [id] => 4833447 [patent_doc_number] => 20080131994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'METHOD FOR MANUFACTURING PHASE CHANGE MEMORY DEVICE WHICH CAN STABLY FORM AN INTERFACE BETWEEN A LOWER ELECTRODE AND A PHASE CHANGE LAYER' [patent_app_type] => utility [patent_app_number] => 11/855664 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2576 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20080131994.pdf [firstpage_image] =>[orig_patent_app_number] => 11855664 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855664
Method for manufacturing phase change memory device which can stably form an interface between a lower electrode and a phase change layer Sep 13, 2007 Issued
Array ( [id] => 62808 [patent_doc_number] => 07763531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Method and structure to process thick and thin fins and variable fin to fin spacing' [patent_app_type] => utility [patent_app_number] => 11/846544 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6136 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763531.pdf [firstpage_image] =>[orig_patent_app_number] => 11846544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846544
Method and structure to process thick and thin fins and variable fin to fin spacing Aug 28, 2007 Issued
Array ( [id] => 4768659 [patent_doc_number] => 20080054315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE BY USING TWO STEP POCKET IMPLANT PROCESS' [patent_app_type] => utility [patent_app_number] => 11/846954 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054315.pdf [firstpage_image] =>[orig_patent_app_number] => 11846954 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846954
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE BY USING TWO STEP POCKET IMPLANT PROCESS Aug 28, 2007 Abandoned
Array ( [id] => 4654922 [patent_doc_number] => 20080023782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'PHOTO SENSOR AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/836080 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2153 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20080023782.pdf [firstpage_image] =>[orig_patent_app_number] => 11836080 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/836080
PHOTO SENSOR AND FABRICATION METHOD THEREOF Aug 7, 2007 Abandoned
Array ( [id] => 177788 [patent_doc_number] => 07655496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-02 [patent_title] => 'Metal lift-off systems and methods using liquid solvent and frozen gas' [patent_app_type] => utility [patent_app_number] => 11/831823 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/655/07655496.pdf [firstpage_image] =>[orig_patent_app_number] => 11831823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831823
Metal lift-off systems and methods using liquid solvent and frozen gas Jul 30, 2007 Issued
Array ( [id] => 22207 [patent_doc_number] => 07799647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'MOSFET device featuring a superlattice barrier layer and method' [patent_app_type] => utility [patent_app_number] => 11/831394 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3255 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/799/07799647.pdf [firstpage_image] =>[orig_patent_app_number] => 11831394 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831394
MOSFET device featuring a superlattice barrier layer and method Jul 30, 2007 Issued
Array ( [id] => 5360728 [patent_doc_number] => 20090035522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Forming electrically isolated conductive traces' [patent_app_type] => utility [patent_app_number] => 11/831640 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035522.pdf [firstpage_image] =>[orig_patent_app_number] => 11831640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831640
Forming electrically isolated conductive traces Jul 30, 2007 Abandoned
Array ( [id] => 4682370 [patent_doc_number] => 20080248596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Method of making a circuitized substrate having at least one capacitor therein' [patent_app_type] => utility [patent_app_number] => 11/878673 [patent_app_country] => US [patent_app_date] => 2007-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15564 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20080248596.pdf [firstpage_image] =>[orig_patent_app_number] => 11878673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/878673
Method of making a circuitized substrate having at least one capacitor therein Jul 25, 2007 Abandoned
Array ( [id] => 4688311 [patent_doc_number] => 20080032492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'METHOD OF MANUFACTURING FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/781623 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20080032492.pdf [firstpage_image] =>[orig_patent_app_number] => 11781623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781623
METHOD OF MANUFACTURING FLASH MEMORY DEVICE Jul 22, 2007 Abandoned
Array ( [id] => 4944123 [patent_doc_number] => 20080081448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/823773 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2811 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20080081448.pdf [firstpage_image] =>[orig_patent_app_number] => 11823773 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/823773
Method for fabricating semiconductor device Jun 27, 2007 Abandoned
Array ( [id] => 4685749 [patent_doc_number] => 20080029930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Production equipment of resin molding semiconductor device, method of manufacturing resin molding semiconductor device, and resin molidng semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/806923 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12329 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029930.pdf [firstpage_image] =>[orig_patent_app_number] => 11806923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/806923
Molded semiconductor device, apparatus for producing the same, and method for manufacturing the same Jun 4, 2007 Issued
Array ( [id] => 4788714 [patent_doc_number] => 20080289687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'METHODS FOR DEPOSITING A SILICON LAYER ON A LASER SCRIBED TRANSMITTING CONDUCTIVE OXIDE LAYER SUITABLE FOR USE IN SOLAR CELL APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 11/752823 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5661 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20080289687.pdf [firstpage_image] =>[orig_patent_app_number] => 11752823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/752823
Silicon layer on a laser transparent conductive oxide layer suitable for use in solar cell applications May 22, 2007 Issued
Array ( [id] => 5085433 [patent_doc_number] => 20070275484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'FERROELECTRIC MEMORY AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/749999 [patent_app_country] => US [patent_app_date] => 2007-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6374 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20070275484.pdf [firstpage_image] =>[orig_patent_app_number] => 11749999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/749999
FERROELECTRIC MEMORY AND METHOD FOR MANUFACTURING THE SAME May 16, 2007 Abandoned
Array ( [id] => 5010893 [patent_doc_number] => 20070281372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'MEMORY ELEMENT, METHOD FOR MANUFACTURING MEMORY ELEMENT, MEMORY DEVICE, ELECTRONIC APPARATUS AND METHOD FOR MANUFACTURING TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/747653 [patent_app_country] => US [patent_app_date] => 2007-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10787 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281372.pdf [firstpage_image] =>[orig_patent_app_number] => 11747653 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/747653
MEMORY ELEMENT, METHOD FOR MANUFACTURING MEMORY ELEMENT, MEMORY DEVICE, ELECTRONIC APPARATUS AND METHOD FOR MANUFACTURING TRANSISTOR May 10, 2007 Abandoned
Array ( [id] => 4839950 [patent_doc_number] => 20080280436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'METHOD FOR FABRICATING AN INDUCTOR STRUCTURE OR A DUAL DAMASCENE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/747214 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 6259 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20080280436.pdf [firstpage_image] =>[orig_patent_app_number] => 11747214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/747214
Method for fabricating an inductor structure or a dual damascene structure May 9, 2007 Issued
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