Pierre E Elisca
Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )
Most Active Art Unit | 3715 |
Art Unit(s) | 3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715 |
Total Applications | 2631 |
Issued Applications | 2140 |
Pending Applications | 221 |
Abandoned Applications | 269 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5225149
[patent_doc_number] => 20070254415
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-01
[patent_title] => 'THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY PANEL INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/741184
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 10187
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0254/20070254415.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741184 | THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY PANEL INCLUDING THE SAME | Apr 26, 2007 | Abandoned |
Array
(
[id] => 5222876
[patent_doc_number] => 20070252142
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-01
[patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/739753
[patent_app_country] => US
[patent_app_date] => 2007-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5744
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20070252142.pdf
[firstpage_image] =>[orig_patent_app_number] => 11739753
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/739753 | Thin film transistor array panel and manufacturing method thereof | Apr 24, 2007 | Issued |
Array
(
[id] => 5210536
[patent_doc_number] => 20070249120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-25
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/785694
[patent_app_country] => US
[patent_app_date] => 2007-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4727
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20070249120.pdf
[firstpage_image] =>[orig_patent_app_number] => 11785694
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/785694 | Nonvolatile semiconductor memory device with multilayer interelectrode dielectric film | Apr 18, 2007 | Issued |
Array
(
[id] => 4873289
[patent_doc_number] => 20080200023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-21
[patent_title] => 'METHOD OF FABRICATING MICRO CONNECTORS'
[patent_app_type] => utility
[patent_app_number] => 11/737134
[patent_app_country] => US
[patent_app_date] => 2007-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 2655
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20080200023.pdf
[firstpage_image] =>[orig_patent_app_number] => 11737134
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/737134 | METHOD OF FABRICATING MICRO CONNECTORS | Apr 17, 2007 | Abandoned |
Array
(
[id] => 8328541
[patent_doc_number] => 08236638
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-07
[patent_title] => 'Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner'
[patent_app_type] => utility
[patent_app_number] => 11/788184
[patent_app_country] => US
[patent_app_date] => 2007-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 24
[patent_no_of_words] => 5339
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11788184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/788184 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner | Apr 17, 2007 | Issued |
Array
(
[id] => 4514174
[patent_doc_number] => 07910455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-22
[patent_title] => 'Method for producing SOI wafer'
[patent_app_type] => utility
[patent_app_number] => 12/226544
[patent_app_country] => US
[patent_app_date] => 2007-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7181
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/910/07910455.pdf
[firstpage_image] =>[orig_patent_app_number] => 12226544
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/226544 | Method for producing SOI wafer | Apr 15, 2007 | Issued |
Array
(
[id] => 7795767
[patent_doc_number] => 08124473
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-28
[patent_title] => 'Strain enhanced semiconductor devices and methods for their fabrication'
[patent_app_type] => utility
[patent_app_number] => 11/734673
[patent_app_country] => US
[patent_app_date] => 2007-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 5474
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/124/08124473.pdf
[firstpage_image] =>[orig_patent_app_number] => 11734673
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/734673 | Strain enhanced semiconductor devices and methods for their fabrication | Apr 11, 2007 | Issued |
Array
(
[id] => 5165618
[patent_doc_number] => 20070287205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-13
[patent_title] => 'METHOD OF MEASURING MINORITY CARRIER DIFFUSION LENGTH AND METHOD OF MANUFACTURING SILICON WAFER'
[patent_app_type] => utility
[patent_app_number] => 11/697796
[patent_app_country] => US
[patent_app_date] => 2007-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4406
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0287/20070287205.pdf
[firstpage_image] =>[orig_patent_app_number] => 11697796
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/697796 | Method of measuring minority carrier diffusion length and method of manufacturing silicon wafer | Apr 8, 2007 | Issued |
Array
(
[id] => 4464185
[patent_doc_number] => 07935607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-03
[patent_title] => 'Integrated passive device with a high resistivity substrate and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/733063
[patent_app_country] => US
[patent_app_date] => 2007-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 3837
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/935/07935607.pdf
[firstpage_image] =>[orig_patent_app_number] => 11733063
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/733063 | Integrated passive device with a high resistivity substrate and method for forming the same | Apr 8, 2007 | Issued |
Array
(
[id] => 4679900
[patent_doc_number] => 20080246126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-09
[patent_title] => 'STACKED AND SHIELDED DIE PACKAGES WITH INTERCONNECTS'
[patent_app_type] => utility
[patent_app_number] => 11/696374
[patent_app_country] => US
[patent_app_date] => 2007-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10072
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20080246126.pdf
[firstpage_image] =>[orig_patent_app_number] => 11696374
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/696374 | STACKED AND SHIELDED DIE PACKAGES WITH INTERCONNECTS | Apr 3, 2007 | Abandoned |
Array
(
[id] => 8104811
[patent_doc_number] => 08154055
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-10
[patent_title] => 'CMOS image sensor and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/730853
[patent_app_country] => US
[patent_app_date] => 2007-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4842
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/154/08154055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11730853
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/730853 | CMOS image sensor and method for fabricating the same | Apr 3, 2007 | Issued |
Array
(
[id] => 5087694
[patent_doc_number] => 20070227333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'TUNING FOLK VIBRATION DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/692365
[patent_app_country] => US
[patent_app_date] => 2007-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3747
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0227/20070227333.pdf
[firstpage_image] =>[orig_patent_app_number] => 11692365
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/692365 | Tuning fork vibration device and method for manufacturing the same | Mar 27, 2007 | Issued |
Array
(
[id] => 4719485
[patent_doc_number] => 20080242008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/691885
[patent_app_country] => US
[patent_app_date] => 2007-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8855
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20080242008.pdf
[firstpage_image] =>[orig_patent_app_number] => 11691885
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/691885 | Method of making three dimensional NAND memory | Mar 26, 2007 | Issued |
Array
(
[id] => 4432644
[patent_doc_number] => 07897505
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-01
[patent_title] => 'Method for enhancing adhesion between layers in BEOL fabrication'
[patent_app_type] => utility
[patent_app_number] => 11/727133
[patent_app_country] => US
[patent_app_date] => 2007-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 3568
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/897/07897505.pdf
[firstpage_image] =>[orig_patent_app_number] => 11727133
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/727133 | Method for enhancing adhesion between layers in BEOL fabrication | Mar 22, 2007 | Issued |
Array
(
[id] => 4740085
[patent_doc_number] => 20080233738
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'METHODS FOR FABRICATING AN INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/689764
[patent_app_country] => US
[patent_app_date] => 2007-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6742
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0233/20080233738.pdf
[firstpage_image] =>[orig_patent_app_number] => 11689764
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/689764 | Methods for fabricating an integrated circuit | Mar 21, 2007 | Issued |
Array
(
[id] => 53731
[patent_doc_number] => 07767504
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-03
[patent_title] => 'Methods for forming film patterns by disposing a liquid within a plural-level partition structure'
[patent_app_type] => utility
[patent_app_number] => 11/689533
[patent_app_country] => US
[patent_app_date] => 2007-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 28
[patent_no_of_words] => 11004
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/767/07767504.pdf
[firstpage_image] =>[orig_patent_app_number] => 11689533
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/689533 | Methods for forming film patterns by disposing a liquid within a plural-level partition structure | Mar 21, 2007 | Issued |
Array
(
[id] => 7773879
[patent_doc_number] => 08119470
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-21
[patent_title] => 'Mitigation of gate to contact capacitance in CMOS flow'
[patent_app_type] => utility
[patent_app_number] => 11/726253
[patent_app_country] => US
[patent_app_date] => 2007-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 3443
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 496
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/119/08119470.pdf
[firstpage_image] =>[orig_patent_app_number] => 11726253
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/726253 | Mitigation of gate to contact capacitance in CMOS flow | Mar 20, 2007 | Issued |
Array
(
[id] => 5063160
[patent_doc_number] => 20070224800
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-27
[patent_title] => 'PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/689133
[patent_app_country] => US
[patent_app_date] => 2007-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6259
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20070224800.pdf
[firstpage_image] =>[orig_patent_app_number] => 11689133
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/689133 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE | Mar 20, 2007 | Abandoned |
Array
(
[id] => 4733913
[patent_doc_number] => 20080050892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-28
[patent_title] => 'Method of manufacturing a thin film structure, method of manufacturing a storage node using the same, method of manufacturing a phase change random access memory using the same and a thin film structure, a storage node and a phase change random access memory formed using the same'
[patent_app_type] => utility
[patent_app_number] => 11/723103
[patent_app_country] => US
[patent_app_date] => 2007-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7377
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0050/20080050892.pdf
[firstpage_image] =>[orig_patent_app_number] => 11723103
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/723103 | Method of manufacturing a thin film structure, method of manufacturing a storage node using the same, method of manufacturing a phase change random access memory using the same and a thin film structure, a storage node and a phase change random access memory formed using the same | Mar 15, 2007 | Abandoned |
Array
(
[id] => 7692075
[patent_doc_number] => 20070231958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'Method of manufacturing a composite electronic part, and composite electronic part'
[patent_app_type] => utility
[patent_app_number] => 11/724643
[patent_app_country] => US
[patent_app_date] => 2007-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8380
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20070231958.pdf
[firstpage_image] =>[orig_patent_app_number] => 11724643
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/724643 | Method of manufacturing a composite electronic part, and composite electronic part | Mar 14, 2007 | Abandoned |