Search

Pierre E Elisca

Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715
Total Applications
2631
Issued Applications
2140
Pending Applications
221
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7796328 [patent_doc_number] => 08125036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Integrated circuit having an edge passivation and oxidation resistant layer and method' [patent_app_type] => utility [patent_app_number] => 11/686154 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10617 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125036.pdf [firstpage_image] =>[orig_patent_app_number] => 11686154 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/686154
Integrated circuit having an edge passivation and oxidation resistant layer and method Mar 13, 2007 Issued
Array ( [id] => 4977341 [patent_doc_number] => 20070218574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Semiconductor laser manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/717676 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4778 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20070218574.pdf [firstpage_image] =>[orig_patent_app_number] => 11717676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717676
Semiconductor laser manufacturing method Mar 13, 2007 Abandoned
Array ( [id] => 5256684 [patent_doc_number] => 20070210316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/683993 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210316.pdf [firstpage_image] =>[orig_patent_app_number] => 11683993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683993
Semiconductor device and manufacturing method thereof with a recessed backside substrate for breakdown voltage blocking Mar 7, 2007 Issued
Array ( [id] => 4685718 [patent_doc_number] => 20080029899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Method of fabricating a semiconductor device and semiconductor device fabricated thereby' [patent_app_type] => utility [patent_app_number] => 11/712504 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029899.pdf [firstpage_image] =>[orig_patent_app_number] => 11712504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/712504
Method of fabricating a semiconductor device and semiconductor device fabricated thereby Feb 28, 2007 Abandoned
Array ( [id] => 341922 [patent_doc_number] => 07501680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Memory device having nanocrystals in memory cell' [patent_app_type] => utility [patent_app_number] => 11/711714 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7574 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501680.pdf [firstpage_image] =>[orig_patent_app_number] => 11711714 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711714
Memory device having nanocrystals in memory cell Feb 27, 2007 Issued
Array ( [id] => 4724029 [patent_doc_number] => 20080203570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD' [patent_app_type] => utility [patent_app_number] => 11/679483 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20080203570.pdf [firstpage_image] =>[orig_patent_app_number] => 11679483 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679483
Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method Feb 26, 2007 Issued
Array ( [id] => 131471 [patent_doc_number] => 07700414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-20 [patent_title] => 'Method of making flip-chip package with underfill' [patent_app_type] => utility [patent_app_number] => 11/709403 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2323 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/700/07700414.pdf [firstpage_image] =>[orig_patent_app_number] => 11709403 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709403
Method of making flip-chip package with underfill Feb 21, 2007 Issued
Array ( [id] => 5005122 [patent_doc_number] => 20070202692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Method for forming silicide and method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/708614 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8536 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20070202692.pdf [firstpage_image] =>[orig_patent_app_number] => 11708614 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708614
Method of nickel disilicide formation and method of nickel disilicate source/drain formation Feb 20, 2007 Issued
Array ( [id] => 311022 [patent_doc_number] => 07528046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/676814 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 9834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528046.pdf [firstpage_image] =>[orig_patent_app_number] => 11676814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/676814
Method for manufacturing semiconductor device Feb 19, 2007 Issued
Array ( [id] => 5385848 [patent_doc_number] => 20090227093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'Patterning During Film Growth' [patent_app_type] => utility [patent_app_number] => 12/223944 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4820 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20090227093.pdf [firstpage_image] =>[orig_patent_app_number] => 12223944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/223944
Patterning During Film Growth Feb 15, 2007 Abandoned
Array ( [id] => 4870754 [patent_doc_number] => 20080197488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'BOWED WAFER HYBRIDIZATION COMPENSATION' [patent_app_type] => utility [patent_app_number] => 11/675453 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197488.pdf [firstpage_image] =>[orig_patent_app_number] => 11675453 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675453
Bowed wafer hybridization compensation Feb 14, 2007 Issued
Array ( [id] => 197474 [patent_doc_number] => 07638799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Image sensor structure with recessed separator layer' [patent_app_type] => utility [patent_app_number] => 11/706194 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2351 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/638/07638799.pdf [firstpage_image] =>[orig_patent_app_number] => 11706194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706194
Image sensor structure with recessed separator layer Feb 14, 2007 Issued
Array ( [id] => 4977376 [patent_doc_number] => 20070218609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/705764 [patent_app_country] => US [patent_app_date] => 2007-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5089 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20070218609.pdf [firstpage_image] =>[orig_patent_app_number] => 11705764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705764
Manufacturing method of semiconductor device Feb 13, 2007 Abandoned
Array ( [id] => 5196715 [patent_doc_number] => 20070296033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Non-volatile memory device having four storage node films and methods of operating and manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/704363 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6189 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20070296033.pdf [firstpage_image] =>[orig_patent_app_number] => 11704363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704363
Non-volatile memory device having four storage node films and methods of operating and manufacturing the same Feb 8, 2007 Abandoned
Array ( [id] => 5069568 [patent_doc_number] => 20070190670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Method of making ferroelectric and dielectric layered superlattice materials and memories utilizing same' [patent_app_type] => utility [patent_app_number] => 11/704623 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9448 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190670.pdf [firstpage_image] =>[orig_patent_app_number] => 11704623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704623
Method of making ferroelectric and dielectric layered superlattice materials and memories utilizing same Feb 8, 2007 Abandoned
Array ( [id] => 5113031 [patent_doc_number] => 20070196946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Method for forming thin film structure and thin film structure, oscillation sensor, pressure sensor, and acceleration sensor' [patent_app_type] => utility [patent_app_number] => 11/703444 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8222 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20070196946.pdf [firstpage_image] =>[orig_patent_app_number] => 11703444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703444
Method of forming thin film structure with tensile and compressed polysilicon layers Feb 6, 2007 Issued
Array ( [id] => 322528 [patent_doc_number] => 07517760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Semiconductor device manufacturing method including three gate insulating films' [patent_app_type] => utility [patent_app_number] => 11/702593 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 37 [patent_no_of_words] => 8306 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517760.pdf [firstpage_image] =>[orig_patent_app_number] => 11702593 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/702593
Semiconductor device manufacturing method including three gate insulating films Feb 5, 2007 Issued
Array ( [id] => 4952698 [patent_doc_number] => 20080185722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Formation process of interconnect structures with air-gaps and sidewall spacers' [patent_app_type] => utility [patent_app_number] => 11/702264 [patent_app_country] => US [patent_app_date] => 2007-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2798 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20080185722.pdf [firstpage_image] =>[orig_patent_app_number] => 11702264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/702264
Formation process of interconnect structures with air-gaps and sidewall spacers Feb 4, 2007 Abandoned
Array ( [id] => 4825881 [patent_doc_number] => 20080124844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHOD OF MANUFACTURING WELL PICK-UP STRUCTURE OF NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/668476 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124844.pdf [firstpage_image] =>[orig_patent_app_number] => 11668476 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668476
Method of manufacturing well pick-up structure of non-volatile memory Jan 29, 2007 Issued
Array ( [id] => 4843302 [patent_doc_number] => 20080179710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'SEMICONDUCTOR WAFER WITH IMPROVED CRACK PROTECTION' [patent_app_type] => utility [patent_app_number] => 11/668453 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179710.pdf [firstpage_image] =>[orig_patent_app_number] => 11668453 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668453
Semiconductor wafer with improved crack protection Jan 28, 2007 Issued
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