Pierre E Elisca
Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )
Most Active Art Unit | 3715 |
Art Unit(s) | 3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715 |
Total Applications | 2631 |
Issued Applications | 2140 |
Pending Applications | 221 |
Abandoned Applications | 269 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7796328
[patent_doc_number] => 08125036
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-28
[patent_title] => 'Integrated circuit having an edge passivation and oxidation resistant layer and method'
[patent_app_type] => utility
[patent_app_number] => 11/686154
[patent_app_country] => US
[patent_app_date] => 2007-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 10617
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/125/08125036.pdf
[firstpage_image] =>[orig_patent_app_number] => 11686154
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/686154 | Integrated circuit having an edge passivation and oxidation resistant layer and method | Mar 13, 2007 | Issued |
Array
(
[id] => 4977341
[patent_doc_number] => 20070218574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'Semiconductor laser manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/717676
[patent_app_country] => US
[patent_app_date] => 2007-03-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0218/20070218574.pdf
[firstpage_image] =>[orig_patent_app_number] => 11717676
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/717676 | Semiconductor laser manufacturing method | Mar 13, 2007 | Abandoned |
Array
(
[id] => 5256684
[patent_doc_number] => 20070210316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-13
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/683993
[patent_app_country] => US
[patent_app_date] => 2007-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0210/20070210316.pdf
[firstpage_image] =>[orig_patent_app_number] => 11683993
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/683993 | Semiconductor device and manufacturing method thereof with a recessed backside substrate for breakdown voltage blocking | Mar 7, 2007 | Issued |
Array
(
[id] => 4685718
[patent_doc_number] => 20080029899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-07
[patent_title] => 'Method of fabricating a semiconductor device and semiconductor device fabricated thereby'
[patent_app_type] => utility
[patent_app_number] => 11/712504
[patent_app_country] => US
[patent_app_date] => 2007-03-01
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 6614
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[firstpage_image] =>[orig_patent_app_number] => 11712504
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/712504 | Method of fabricating a semiconductor device and semiconductor device fabricated thereby | Feb 28, 2007 | Abandoned |
Array
(
[id] => 341922
[patent_doc_number] => 07501680
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-10
[patent_title] => 'Memory device having nanocrystals in memory cell'
[patent_app_type] => utility
[patent_app_number] => 11/711714
[patent_app_country] => US
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[pdf_file] => patents/07/501/07501680.pdf
[firstpage_image] =>[orig_patent_app_number] => 11711714
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/711714 | Memory device having nanocrystals in memory cell | Feb 27, 2007 | Issued |
Array
(
[id] => 4724029
[patent_doc_number] => 20080203570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/679483
[patent_app_country] => US
[patent_app_date] => 2007-02-27
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[pdf_file] => publications/A1/0203/20080203570.pdf
[firstpage_image] =>[orig_patent_app_number] => 11679483
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/679483 | Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method | Feb 26, 2007 | Issued |
Array
(
[id] => 131471
[patent_doc_number] => 07700414
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-04-20
[patent_title] => 'Method of making flip-chip package with underfill'
[patent_app_type] => utility
[patent_app_number] => 11/709403
[patent_app_country] => US
[patent_app_date] => 2007-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2323
[patent_no_of_claims] => 12
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[pdf_file] => patents/07/700/07700414.pdf
[firstpage_image] =>[orig_patent_app_number] => 11709403
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/709403 | Method of making flip-chip package with underfill | Feb 21, 2007 | Issued |
Array
(
[id] => 5005122
[patent_doc_number] => 20070202692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-30
[patent_title] => 'Method for forming silicide and method for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/708614
[patent_app_country] => US
[patent_app_date] => 2007-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 8536
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[pdf_file] => publications/A1/0202/20070202692.pdf
[firstpage_image] =>[orig_patent_app_number] => 11708614
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/708614 | Method of nickel disilicide formation and method of nickel disilicate source/drain formation | Feb 20, 2007 | Issued |
Array
(
[id] => 311022
[patent_doc_number] => 07528046
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/676814
[patent_app_country] => US
[patent_app_date] => 2007-02-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/528/07528046.pdf
[firstpage_image] =>[orig_patent_app_number] => 11676814
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/676814 | Method for manufacturing semiconductor device | Feb 19, 2007 | Issued |
Array
(
[id] => 5385848
[patent_doc_number] => 20090227093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-10
[patent_title] => 'Patterning During Film Growth'
[patent_app_type] => utility
[patent_app_number] => 12/223944
[patent_app_country] => US
[patent_app_date] => 2007-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 4820
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[pdf_file] => publications/A1/0227/20090227093.pdf
[firstpage_image] =>[orig_patent_app_number] => 12223944
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/223944 | Patterning During Film Growth | Feb 15, 2007 | Abandoned |
Array
(
[id] => 4870754
[patent_doc_number] => 20080197488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-21
[patent_title] => 'BOWED WAFER HYBRIDIZATION COMPENSATION'
[patent_app_type] => utility
[patent_app_number] => 11/675453
[patent_app_country] => US
[patent_app_date] => 2007-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0197/20080197488.pdf
[firstpage_image] =>[orig_patent_app_number] => 11675453
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/675453 | Bowed wafer hybridization compensation | Feb 14, 2007 | Issued |
Array
(
[id] => 197474
[patent_doc_number] => 07638799
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-29
[patent_title] => 'Image sensor structure with recessed separator layer'
[patent_app_type] => utility
[patent_app_number] => 11/706194
[patent_app_country] => US
[patent_app_date] => 2007-02-15
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[firstpage_image] =>[orig_patent_app_number] => 11706194
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/706194 | Image sensor structure with recessed separator layer | Feb 14, 2007 | Issued |
Array
(
[id] => 4977376
[patent_doc_number] => 20070218609
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'Manufacturing method of semiconductor device'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11705764
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/705764 | Manufacturing method of semiconductor device | Feb 13, 2007 | Abandoned |
Array
(
[id] => 5196715
[patent_doc_number] => 20070296033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-27
[patent_title] => 'Non-volatile memory device having four storage node films and methods of operating and manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/704363
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/704363 | Non-volatile memory device having four storage node films and methods of operating and manufacturing the same | Feb 8, 2007 | Abandoned |
Array
(
[id] => 5069568
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[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-16
[patent_title] => 'Method of making ferroelectric and dielectric layered superlattice materials and memories utilizing same'
[patent_app_type] => utility
[patent_app_number] => 11/704623
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/704623 | Method of making ferroelectric and dielectric layered superlattice materials and memories utilizing same | Feb 8, 2007 | Abandoned |
Array
(
[id] => 5113031
[patent_doc_number] => 20070196946
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[patent_issue_date] => 2007-08-23
[patent_title] => 'Method for forming thin film structure and thin film structure, oscillation sensor, pressure sensor, and acceleration sensor'
[patent_app_type] => utility
[patent_app_number] => 11/703444
[patent_app_country] => US
[patent_app_date] => 2007-02-07
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[firstpage_image] =>[orig_patent_app_number] => 11703444
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/703444 | Method of forming thin film structure with tensile and compressed polysilicon layers | Feb 6, 2007 | Issued |
Array
(
[id] => 322528
[patent_doc_number] => 07517760
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[patent_issue_date] => 2009-04-14
[patent_title] => 'Semiconductor device manufacturing method including three gate insulating films'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/702593 | Semiconductor device manufacturing method including three gate insulating films | Feb 5, 2007 | Issued |
Array
(
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[patent_title] => 'Formation process of interconnect structures with air-gaps and sidewall spacers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/702264 | Formation process of interconnect structures with air-gaps and sidewall spacers | Feb 4, 2007 | Abandoned |
Array
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[patent_title] => 'METHOD OF MANUFACTURING WELL PICK-UP STRUCTURE OF NON-VOLATILE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/668476
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[firstpage_image] =>[orig_patent_app_number] => 11668476
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/668476 | Method of manufacturing well pick-up structure of non-volatile memory | Jan 29, 2007 | Issued |
Array
(
[id] => 4843302
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[patent_issue_date] => 2008-07-31
[patent_title] => 'SEMICONDUCTOR WAFER WITH IMPROVED CRACK PROTECTION'
[patent_app_type] => utility
[patent_app_number] => 11/668453
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[firstpage_image] =>[orig_patent_app_number] => 11668453
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/668453 | Semiconductor wafer with improved crack protection | Jan 28, 2007 | Issued |