Search

Pierre E Elisca

Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715
Total Applications
2631
Issued Applications
2140
Pending Applications
221
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5175139 [patent_doc_number] => 20070176197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Semiconductor device and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/699034 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4817 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176197.pdf [firstpage_image] =>[orig_patent_app_number] => 11699034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699034
Semiconductor device and method of manufacturing semiconductor device Jan 28, 2007 Abandoned
Array ( [id] => 162235 [patent_doc_number] => 07670861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Controlling stress in MEMS structures' [patent_app_type] => utility [patent_app_number] => 11/698023 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6248 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/670/07670861.pdf [firstpage_image] =>[orig_patent_app_number] => 11698023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698023
Controlling stress in MEMS structures Jan 25, 2007 Issued
Array ( [id] => 4765134 [patent_doc_number] => 20080176345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes' [patent_app_type] => utility [patent_app_number] => 11/655483 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4143 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20080176345.pdf [firstpage_image] =>[orig_patent_app_number] => 11655483 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655483
Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes Jan 18, 2007 Abandoned
Array ( [id] => 4762708 [patent_doc_number] => 20080173917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Selective deposition method' [patent_app_type] => utility [patent_app_number] => 11/655664 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2872 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20080173917.pdf [firstpage_image] =>[orig_patent_app_number] => 11655664 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655664
Selective deposition method Jan 18, 2007 Abandoned
Array ( [id] => 4762763 [patent_doc_number] => 20080173972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'METHOD OF WAFER THINNING' [patent_app_type] => utility [patent_app_number] => 11/624824 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1887 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20080173972.pdf [firstpage_image] =>[orig_patent_app_number] => 11624824 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/624824
METHOD OF WAFER THINNING Jan 18, 2007 Abandoned
Array ( [id] => 5188625 [patent_doc_number] => 20070166933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Methods of Forming Field Effect Transistors and Capacitor-Free Dynamic Random Access Memory Cells' [patent_app_type] => utility [patent_app_number] => 11/622584 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2810 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166933.pdf [firstpage_image] =>[orig_patent_app_number] => 11622584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/622584
Methods of forming field effect transistors and capacitor-free dynamic random access memory cells Jan 11, 2007 Issued
Array ( [id] => 369815 [patent_doc_number] => 07476588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Methods of forming NAND cell units with string gates of various widths' [patent_app_type] => utility [patent_app_number] => 11/652903 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3910 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/476/07476588.pdf [firstpage_image] =>[orig_patent_app_number] => 11652903 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652903
Methods of forming NAND cell units with string gates of various widths Jan 11, 2007 Issued
Array ( [id] => 348771 [patent_doc_number] => 07494886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Uniaxial strain relaxation of biaxial-strained thin films using ion implantation' [patent_app_type] => utility [patent_app_number] => 11/622524 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3810 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494886.pdf [firstpage_image] =>[orig_patent_app_number] => 11622524 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/622524
Uniaxial strain relaxation of biaxial-strained thin films using ion implantation Jan 11, 2007 Issued
Array ( [id] => 5066606 [patent_doc_number] => 20070187707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Semiconductor device and production method thereof' [patent_app_type] => utility [patent_app_number] => 11/651534 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3334 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20070187707.pdf [firstpage_image] =>[orig_patent_app_number] => 11651534 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651534
Method of producing a semiconductor device by forming an oxide film on a resin layer Jan 9, 2007 Issued
Array ( [id] => 5005086 [patent_doc_number] => 20070202656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/651523 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20070202656.pdf [firstpage_image] =>[orig_patent_app_number] => 11651523 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651523
Method of fabricating a semiconductor device Jan 9, 2007 Issued
Array ( [id] => 5185767 [patent_doc_number] => 20070164073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Wafer dividing method and wafer dividing apparatus' [patent_app_type] => utility [patent_app_number] => 11/650503 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4543 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20070164073.pdf [firstpage_image] =>[orig_patent_app_number] => 11650503 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/650503
Wafer dividing method and wafer dividing apparatus Jan 7, 2007 Issued
Array ( [id] => 4988694 [patent_doc_number] => 20070155033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Method of manufacturing light emitting diode package' [patent_app_type] => utility [patent_app_number] => 11/649914 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2619 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20070155033.pdf [firstpage_image] =>[orig_patent_app_number] => 11649914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/649914
Method of manufacturing light emitting diode package Jan 4, 2007 Abandoned
Array ( [id] => 4925254 [patent_doc_number] => 20080164617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Method of Forming Vertical Contacts in Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 11/619623 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20080164617.pdf [firstpage_image] =>[orig_patent_app_number] => 11619623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619623
Method of forming vertical contacts in integrated circuits Jan 3, 2007 Issued
Array ( [id] => 4752677 [patent_doc_number] => 20080160752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD FOR CHIP TO PACKAGE INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 11/619384 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1663 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20080160752.pdf [firstpage_image] =>[orig_patent_app_number] => 11619384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619384
METHOD FOR CHIP TO PACKAGE INTERCONNECT Jan 2, 2007 Abandoned
Array ( [id] => 348712 [patent_doc_number] => 07494825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Top contact alignment in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/649094 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2757 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494825.pdf [firstpage_image] =>[orig_patent_app_number] => 11649094 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/649094
Top contact alignment in semiconductor devices Jan 2, 2007 Issued
Array ( [id] => 4932992 [patent_doc_number] => 20080003767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/647813 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1892 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003767.pdf [firstpage_image] =>[orig_patent_app_number] => 11647813 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647813
Method for fabricating semiconductor device Dec 28, 2006 Abandoned
Array ( [id] => 4932969 [patent_doc_number] => 20080003744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'METHOD OF MANUFACTURING NAND FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/618714 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2044 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003744.pdf [firstpage_image] =>[orig_patent_app_number] => 11618714 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618714
METHOD OF MANUFACTURING NAND FLASH MEMORY DEVICE Dec 28, 2006 Abandoned
Array ( [id] => 5188627 [patent_doc_number] => 20070166935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Method of fabricating nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 11/647864 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2645 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166935.pdf [firstpage_image] =>[orig_patent_app_number] => 11647864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647864
Method of fabricating nonvolatile memory device Dec 27, 2006 Abandoned
Array ( [id] => 7692014 [patent_doc_number] => 20070232019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Method for forming isolation structure in nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 11/647634 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3004 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232019.pdf [firstpage_image] =>[orig_patent_app_number] => 11647634 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647634
Method for forming isolation structure in nonvolatile memory device Dec 27, 2006 Abandoned
Array ( [id] => 4825872 [patent_doc_number] => 20080124836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Packaging substrate and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/646244 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2578 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124836.pdf [firstpage_image] =>[orig_patent_app_number] => 11646244 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646244
Packaging substrate and manufacturing method thereof Dec 27, 2006 Issued
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