Search

Pierre E Elisca

Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715
Total Applications
2631
Issued Applications
2140
Pending Applications
221
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4749294 [patent_doc_number] => 20080157365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor' [patent_app_type] => utility [patent_app_number] => 11/646764 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9302 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157365.pdf [firstpage_image] =>[orig_patent_app_number] => 11646764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646764
Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate Dec 26, 2006 Issued
Array ( [id] => 5098753 [patent_doc_number] => 20070182013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Damascene structure having a reduced permittivity and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/645624 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3373 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20070182013.pdf [firstpage_image] =>[orig_patent_app_number] => 11645624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645624
Damascene structure having a reduced permittivity and manufacturing method thereof Dec 26, 2006 Issued
Array ( [id] => 587398 [patent_doc_number] => 07439175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Method for fabricating a thin film and metal line of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/645533 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2204 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/439/07439175.pdf [firstpage_image] =>[orig_patent_app_number] => 11645533 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645533
Method for fabricating a thin film and metal line of semiconductor device Dec 26, 2006 Issued
Array ( [id] => 5219911 [patent_doc_number] => 20070161222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'METHOD OF FORMING PAD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/616734 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 1094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20070161222.pdf [firstpage_image] =>[orig_patent_app_number] => 11616734 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616734
METHOD OF FORMING PAD OF SEMICONDUCTOR DEVICE Dec 26, 2006 Abandoned
Array ( [id] => 5219941 [patent_doc_number] => 20070161252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Method of manufacturing flash memory and flash memory manufactured from the method' [patent_app_type] => utility [patent_app_number] => 11/645504 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2962 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20070161252.pdf [firstpage_image] =>[orig_patent_app_number] => 11645504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645504
Method of manufacturing flash memory and flash memory manufactured from the method Dec 26, 2006 Abandoned
Array ( [id] => 5230918 [patent_doc_number] => 20070293026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/616023 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2128 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20070293026.pdf [firstpage_image] =>[orig_patent_app_number] => 11616023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616023
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Dec 25, 2006 Abandoned
Array ( [id] => 5019470 [patent_doc_number] => 20070145436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Thin film transistor substrate of liquid crystal display and method for fabricating same' [patent_app_type] => utility [patent_app_number] => 11/645434 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2724 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145436.pdf [firstpage_image] =>[orig_patent_app_number] => 11645434 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645434
Thin film transistor substrate of liquid crystal display and method for fabricating same Dec 25, 2006 Abandoned
Array ( [id] => 32564 [patent_doc_number] => 07790605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Formation of interconnects through lift-off processing' [patent_app_type] => utility [patent_app_number] => 11/644834 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5342 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790605.pdf [firstpage_image] =>[orig_patent_app_number] => 11644834 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644834
Formation of interconnects through lift-off processing Dec 25, 2006 Issued
Array ( [id] => 5219943 [patent_doc_number] => 20070161254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'METHOD OF FORMING A PASSIVATION LAYER OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/616253 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1151 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20070161254.pdf [firstpage_image] =>[orig_patent_app_number] => 11616253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616253
METHOD OF FORMING A PASSIVATION LAYER OF A SEMICONDUCTOR DEVICE Dec 25, 2006 Abandoned
Array ( [id] => 4876619 [patent_doc_number] => 20080150002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Simultaneous Formation of a Top Oxide Layer in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Transistor and a Gate Oxide in a Metal Oxide Semiconductor (MOS)' [patent_app_type] => utility [patent_app_number] => 11/615683 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4881 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150002.pdf [firstpage_image] =>[orig_patent_app_number] => 11615683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615683
Simultaneous Formation of a Top Oxide Layer in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Transistor and a Gate Oxide in a Metal Oxide Semiconductor (MOS) Dec 21, 2006 Abandoned
Array ( [id] => 4876762 [patent_doc_number] => 20080150145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Adhesion and electromigration performance at an interface between a dielectric and metal' [patent_app_type] => utility [patent_app_number] => 11/644743 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150145.pdf [firstpage_image] =>[orig_patent_app_number] => 11644743 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644743
Adhesion and electromigration performance at an interface between a dielectric and metal Dec 20, 2006 Issued
Array ( [id] => 5022932 [patent_doc_number] => 20070148898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method for Forming Capacitor' [patent_app_type] => utility [patent_app_number] => 11/613215 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3694 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148898.pdf [firstpage_image] =>[orig_patent_app_number] => 11613215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613215
Method for Forming Capacitor Dec 19, 2006 Abandoned
Array ( [id] => 4863800 [patent_doc_number] => 20080142859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Methods of forming ferroelectric media with patterned nano structures for data storage devices' [patent_app_type] => utility [patent_app_number] => 11/643263 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2629 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20080142859.pdf [firstpage_image] =>[orig_patent_app_number] => 11643263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643263
Methods of forming ferroelectric media with patterned nano structures for data storage devices Dec 18, 2006 Abandoned
Array ( [id] => 602430 [patent_doc_number] => 07432193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Method for fabricating a thin film and a metal line of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/640916 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2576 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432193.pdf [firstpage_image] =>[orig_patent_app_number] => 11640916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/640916
Method for fabricating a thin film and a metal line of a semiconductor device Dec 18, 2006 Issued
Array ( [id] => 7796304 [patent_doc_number] => 08125012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Non-volatile memory device with a silicon nitride charge holding film having an excess of silicon' [patent_app_type] => utility [patent_app_number] => 11/639134 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 15392 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125012.pdf [firstpage_image] =>[orig_patent_app_number] => 11639134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/639134
Non-volatile memory device with a silicon nitride charge holding film having an excess of silicon Dec 14, 2006 Issued
Array ( [id] => 800326 [patent_doc_number] => 07425468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Method for making flip chip on leadframe package' [patent_app_type] => utility [patent_app_number] => 11/636995 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 2710 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425468.pdf [firstpage_image] =>[orig_patent_app_number] => 11636995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636995
Method for making flip chip on leadframe package Dec 11, 2006 Issued
Array ( [id] => 7796325 [patent_doc_number] => 08125033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Polycrystalline silicon layer, flat panel display using the same, and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/636962 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 5458 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125033.pdf [firstpage_image] =>[orig_patent_app_number] => 11636962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636962
Polycrystalline silicon layer, flat panel display using the same, and method of fabricating the same Dec 11, 2006 Issued
Array ( [id] => 5250477 [patent_doc_number] => 20070131933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Polycrystalline silicon layer, flat panel display using the same, and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/636964 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5174 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20070131933.pdf [firstpage_image] =>[orig_patent_app_number] => 11636964 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636964
Polycrystalline silicon layer, flat panel display using the same, and methods of fabricating the same Dec 11, 2006 Issued
Array ( [id] => 5253470 [patent_doc_number] => 20070134926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Method of etching for multi-layered structure of semiconductors in groups III-V and method for manufacturing vertical cavity surface emitting laser device' [patent_app_type] => utility [patent_app_number] => 11/635223 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3558 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20070134926.pdf [firstpage_image] =>[orig_patent_app_number] => 11635223 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/635223
Method of etching for multi-layered structure of semiconductors in group III-V and method for manufacturing vertical cavity surface emitting laser device Dec 6, 2006 Issued
Array ( [id] => 588957 [patent_doc_number] => 07435618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Method to manufacture a coreless packaging substrate' [patent_app_type] => utility [patent_app_number] => 11/635034 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 2435 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/435/07435618.pdf [firstpage_image] =>[orig_patent_app_number] => 11635034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/635034
Method to manufacture a coreless packaging substrate Dec 6, 2006 Issued
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