Pierre E Elisca
Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )
Most Active Art Unit | 3715 |
Art Unit(s) | 3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715 |
Total Applications | 2631 |
Issued Applications | 2140 |
Pending Applications | 221 |
Abandoned Applications | 269 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4749294
[patent_doc_number] => 20080157365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/646764
[patent_app_country] => US
[patent_app_date] => 2006-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20080157365.pdf
[firstpage_image] =>[orig_patent_app_number] => 11646764
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/646764 | Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate | Dec 26, 2006 | Issued |
Array
(
[id] => 5098753
[patent_doc_number] => 20070182013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-09
[patent_title] => 'Damascene structure having a reduced permittivity and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/645624
[patent_app_country] => US
[patent_app_date] => 2006-12-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0182/20070182013.pdf
[firstpage_image] =>[orig_patent_app_number] => 11645624
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/645624 | Damascene structure having a reduced permittivity and manufacturing method thereof | Dec 26, 2006 | Issued |
Array
(
[id] => 587398
[patent_doc_number] => 07439175
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-21
[patent_title] => 'Method for fabricating a thin film and metal line of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/645533
[patent_app_country] => US
[patent_app_date] => 2006-12-27
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[pdf_file] => patents/07/439/07439175.pdf
[firstpage_image] =>[orig_patent_app_number] => 11645533
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/645533 | Method for fabricating a thin film and metal line of semiconductor device | Dec 26, 2006 | Issued |
Array
(
[id] => 5219911
[patent_doc_number] => 20070161222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'METHOD OF FORMING PAD OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/616734
[patent_app_country] => US
[patent_app_date] => 2006-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[firstpage_image] =>[orig_patent_app_number] => 11616734
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616734 | METHOD OF FORMING PAD OF SEMICONDUCTOR DEVICE | Dec 26, 2006 | Abandoned |
Array
(
[id] => 5219941
[patent_doc_number] => 20070161252
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[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'Method of manufacturing flash memory and flash memory manufactured from the method'
[patent_app_type] => utility
[patent_app_number] => 11/645504
[patent_app_country] => US
[patent_app_date] => 2006-12-27
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[pdf_file] => publications/A1/0161/20070161252.pdf
[firstpage_image] =>[orig_patent_app_number] => 11645504
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/645504 | Method of manufacturing flash memory and flash memory manufactured from the method | Dec 26, 2006 | Abandoned |
Array
(
[id] => 5230918
[patent_doc_number] => 20070293026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/616023
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[pdf_file] => publications/A1/0293/20070293026.pdf
[firstpage_image] =>[orig_patent_app_number] => 11616023
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616023 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Dec 25, 2006 | Abandoned |
Array
(
[id] => 5019470
[patent_doc_number] => 20070145436
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Thin film transistor substrate of liquid crystal display and method for fabricating same'
[patent_app_type] => utility
[patent_app_number] => 11/645434
[patent_app_country] => US
[patent_app_date] => 2006-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2724
[patent_no_of_claims] => 17
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[pdf_file] => publications/A1/0145/20070145436.pdf
[firstpage_image] =>[orig_patent_app_number] => 11645434
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/645434 | Thin film transistor substrate of liquid crystal display and method for fabricating same | Dec 25, 2006 | Abandoned |
Array
(
[id] => 32564
[patent_doc_number] => 07790605
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'Formation of interconnects through lift-off processing'
[patent_app_type] => utility
[patent_app_number] => 11/644834
[patent_app_country] => US
[patent_app_date] => 2006-12-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/790/07790605.pdf
[firstpage_image] =>[orig_patent_app_number] => 11644834
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/644834 | Formation of interconnects through lift-off processing | Dec 25, 2006 | Issued |
Array
(
[id] => 5219943
[patent_doc_number] => 20070161254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'METHOD OF FORMING A PASSIVATION LAYER OF A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/616253
[patent_app_country] => US
[patent_app_date] => 2006-12-26
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0161/20070161254.pdf
[firstpage_image] =>[orig_patent_app_number] => 11616253
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616253 | METHOD OF FORMING A PASSIVATION LAYER OF A SEMICONDUCTOR DEVICE | Dec 25, 2006 | Abandoned |
Array
(
[id] => 4876619
[patent_doc_number] => 20080150002
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Simultaneous Formation of a Top Oxide Layer in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Transistor and a Gate Oxide in a Metal Oxide Semiconductor (MOS)'
[patent_app_type] => utility
[patent_app_number] => 11/615683
[patent_app_country] => US
[patent_app_date] => 2006-12-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0150/20080150002.pdf
[firstpage_image] =>[orig_patent_app_number] => 11615683
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615683 | Simultaneous Formation of a Top Oxide Layer in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Transistor and a Gate Oxide in a Metal Oxide Semiconductor (MOS) | Dec 21, 2006 | Abandoned |
Array
(
[id] => 4876762
[patent_doc_number] => 20080150145
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Adhesion and electromigration performance at an interface between a dielectric and metal'
[patent_app_type] => utility
[patent_app_number] => 11/644743
[patent_app_country] => US
[patent_app_date] => 2006-12-21
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[patent_drawing_sheets_cnt] => 11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/644743 | Adhesion and electromigration performance at an interface between a dielectric and metal | Dec 20, 2006 | Issued |
Array
(
[id] => 5022932
[patent_doc_number] => 20070148898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Method for Forming Capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/613215
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11613215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/613215 | Method for Forming Capacitor | Dec 19, 2006 | Abandoned |
Array
(
[id] => 4863800
[patent_doc_number] => 20080142859
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[patent_kind] => A1
[patent_issue_date] => 2008-06-19
[patent_title] => 'Methods of forming ferroelectric media with patterned nano structures for data storage devices'
[patent_app_type] => utility
[patent_app_number] => 11/643263
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/643263 | Methods of forming ferroelectric media with patterned nano structures for data storage devices | Dec 18, 2006 | Abandoned |
Array
(
[id] => 602430
[patent_doc_number] => 07432193
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[patent_title] => 'Method for fabricating a thin film and a metal line of a semiconductor device'
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Array
(
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[patent_title] => 'Non-volatile memory device with a silicon nitride charge holding film having an excess of silicon'
[patent_app_type] => utility
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Array
(
[id] => 800326
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[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-16
[patent_title] => 'Method for making flip chip on leadframe package'
[patent_app_type] => utility
[patent_app_number] => 11/636995
[patent_app_country] => US
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Array
(
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[patent_issue_date] => 2012-02-28
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Array
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Array
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Array
(
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[patent_issue_date] => 2008-10-14
[patent_title] => 'Method to manufacture a coreless packaging substrate'
[patent_app_type] => utility
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11635034
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/635034 | Method to manufacture a coreless packaging substrate | Dec 6, 2006 | Issued |