Pierre E Elisca
Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )
Most Active Art Unit | 3715 |
Art Unit(s) | 3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715 |
Total Applications | 2631 |
Issued Applications | 2140 |
Pending Applications | 221 |
Abandoned Applications | 269 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5605521
[patent_doc_number] => 20060267037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'Light emitting diode package'
[patent_app_type] => utility
[patent_app_number] => 11/442964
[patent_app_country] => US
[patent_app_date] => 2006-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2869
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20060267037.pdf
[firstpage_image] =>[orig_patent_app_number] => 11442964
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/442964 | Light emitting diode package | May 30, 2006 | Abandoned |
Array
(
[id] => 23310
[patent_doc_number] => 07800187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Trech-type vertical semiconductor device having gate electrode buried in rounded hump opening'
[patent_app_type] => utility
[patent_app_number] => 11/435754
[patent_app_country] => US
[patent_app_date] => 2006-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 3605
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/800/07800187.pdf
[firstpage_image] =>[orig_patent_app_number] => 11435754
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/435754 | Trech-type vertical semiconductor device having gate electrode buried in rounded hump opening | May 17, 2006 | Issued |
Array
(
[id] => 5605595
[patent_doc_number] => 20060267111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'Double-gate FETs (Field Effect Transistors)'
[patent_app_type] => utility
[patent_app_number] => 11/436480
[patent_app_country] => US
[patent_app_date] => 2006-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 3575
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20060267111.pdf
[firstpage_image] =>[orig_patent_app_number] => 11436480
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/436480 | Double-gate FETs (field effect transistors) | May 17, 2006 | Issued |
Array
(
[id] => 5046101
[patent_doc_number] => 20070264774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'Method of Manufacturing a Flash Memory Device'
[patent_app_type] => utility
[patent_app_number] => 11/383073
[patent_app_country] => US
[patent_app_date] => 2006-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 3946
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20070264774.pdf
[firstpage_image] =>[orig_patent_app_number] => 11383073
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/383073 | Method of manufacturing a memory device | May 11, 2006 | Issued |
Array
(
[id] => 4597069
[patent_doc_number] => 07982252
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-19
[patent_title] => 'Dual-gate non-volatile ferroelectric memory'
[patent_app_type] => utility
[patent_app_number] => 11/433753
[patent_app_country] => US
[patent_app_date] => 2006-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 29
[patent_no_of_words] => 8624
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/982/07982252.pdf
[firstpage_image] =>[orig_patent_app_number] => 11433753
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/433753 | Dual-gate non-volatile ferroelectric memory | May 10, 2006 | Issued |
Array
(
[id] => 92001
[patent_doc_number] => 07732312
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-08
[patent_title] => 'FUSI integration method using SOG as a sacrificial planarization layer'
[patent_app_type] => utility
[patent_app_number] => 11/338028
[patent_app_country] => US
[patent_app_date] => 2006-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 5180
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/732/07732312.pdf
[firstpage_image] =>[orig_patent_app_number] => 11338028
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/338028 | FUSI integration method using SOG as a sacrificial planarization layer | Jan 23, 2006 | Issued |
Array
(
[id] => 5874538
[patent_doc_number] => 20060166442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/338269
[patent_app_country] => US
[patent_app_date] => 2006-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3038
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0166/20060166442.pdf
[firstpage_image] =>[orig_patent_app_number] => 11338269
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/338269 | Method for manufacturing semiconductor device | Jan 23, 2006 | Abandoned |
Array
(
[id] => 5159982
[patent_doc_number] => 20070173026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-26
[patent_title] => 'Method for fabricating bipolar integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/336899
[patent_app_country] => US
[patent_app_date] => 2006-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 3035
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20070173026.pdf
[firstpage_image] =>[orig_patent_app_number] => 11336899
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/336899 | Method for fabricating bipolar integrated circuits | Jan 22, 2006 | Abandoned |
Array
(
[id] => 5188615
[patent_doc_number] => 20070166923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Method for nitridation of the interface between a dielectric and a substrate in a MOS device'
[patent_app_type] => utility
[patent_app_number] => 11/334249
[patent_app_country] => US
[patent_app_date] => 2006-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2320
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0166/20070166923.pdf
[firstpage_image] =>[orig_patent_app_number] => 11334249
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/334249 | Method for nitridation of the interface between a dielectric and a substrate in a MOS device | Jan 17, 2006 | Issued |
Array
(
[id] => 10888018
[patent_doc_number] => 08912014
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-12-16
[patent_title] => 'Controlling the latchup effect'
[patent_app_type] => utility
[patent_app_number] => 11/333208
[patent_app_country] => US
[patent_app_date] => 2006-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5106
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11333208
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/333208 | Controlling the latchup effect | Jan 17, 2006 | Issued |
Array
(
[id] => 10897979
[patent_doc_number] => 08921193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-30
[patent_title] => 'Pre-gate dielectric process using hydrogen annealing'
[patent_app_type] => utility
[patent_app_number] => 11/333399
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2421
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11333399
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/333399 | Pre-gate dielectric process using hydrogen annealing | Jan 16, 2006 | Issued |
Array
(
[id] => 5677922
[patent_doc_number] => 20060183278
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-17
[patent_title] => 'Field effect device having a channel of nanofabric and methods of making same'
[patent_app_type] => utility
[patent_app_number] => 11/332529
[patent_app_country] => US
[patent_app_date] => 2006-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 8755
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20060183278.pdf
[firstpage_image] =>[orig_patent_app_number] => 11332529
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/332529 | Field effect device having a channel of nanofabric and methods of making same | Jan 12, 2006 | Issued |
Array
(
[id] => 5159996
[patent_doc_number] => 20070173040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-26
[patent_title] => 'Method of reducing an inter-atomic bond strength in a substance'
[patent_app_type] => utility
[patent_app_number] => 11/329324
[patent_app_country] => US
[patent_app_date] => 2006-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7277
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20070173040.pdf
[firstpage_image] =>[orig_patent_app_number] => 11329324
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/329324 | Method of reducing an inter-atomic bond strength in a substance | Jan 8, 2006 | Abandoned |
Array
(
[id] => 5785728
[patent_doc_number] => 20060205224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-14
[patent_title] => 'Large-scale trimming for ultra-narrow gates'
[patent_app_type] => utility
[patent_app_number] => 11/318934
[patent_app_country] => US
[patent_app_date] => 2005-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4590
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20060205224.pdf
[firstpage_image] =>[orig_patent_app_number] => 11318934
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/318934 | Large-scale trimming for ultra-narrow gates | Dec 26, 2005 | Abandoned |
Array
(
[id] => 5683097
[patent_doc_number] => 20060199367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/164824
[patent_app_country] => US
[patent_app_date] => 2005-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3065
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20060199367.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164824
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164824 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Dec 6, 2005 | Abandoned |
Array
(
[id] => 7689399
[patent_doc_number] => 20070105299
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 11/164114
[patent_app_country] => US
[patent_app_date] => 2005-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1918
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0105/20070105299.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164114
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164114 | Dual stress memory technique method and related structure | Nov 9, 2005 | Issued |
Array
(
[id] => 5608616
[patent_doc_number] => 20060270132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'Manufacturing process and structure of power junction field effect transistor'
[patent_app_type] => utility
[patent_app_number] => 11/194847
[patent_app_country] => US
[patent_app_date] => 2005-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2755
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20060270132.pdf
[firstpage_image] =>[orig_patent_app_number] => 11194847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/194847 | Manufacturing process and structure of power junction field effect transistor | Jul 31, 2005 | Abandoned |
Array
(
[id] => 7248039
[patent_doc_number] => 20050272220
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-08
[patent_title] => 'Ultraviolet curing process for spin-on dielectric materials used in pre-metal and/or shallow trench isolation applications'
[patent_app_type] => utility
[patent_app_number] => 11/146744
[patent_app_country] => US
[patent_app_date] => 2005-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3659
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0272/20050272220.pdf
[firstpage_image] =>[orig_patent_app_number] => 11146744
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/146744 | Ultraviolet curing process for spin-on dielectric materials used in pre-metal and/or shallow trench isolation applications | Jun 6, 2005 | Abandoned |
Array
(
[id] => 4796636
[patent_doc_number] => 20080008222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'Laser Irradiation Method and Apparatus, Method for Annealing Non-Single Cyrstal, and Method for Manufacturing Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 11/596583
[patent_app_country] => US
[patent_app_date] => 2005-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8386
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0008/20080008222.pdf
[firstpage_image] =>[orig_patent_app_number] => 11596583
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/596583 | Laser annealing method wherein reflected beams are minimized | Jun 5, 2005 | Issued |
Array
(
[id] => 7185694
[patent_doc_number] => 20050191851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Barrier metal cap structure on copper lines and vias'
[patent_app_type] => utility
[patent_app_number] => 11/119274
[patent_app_country] => US
[patent_app_date] => 2005-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3756
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20050191851.pdf
[firstpage_image] =>[orig_patent_app_number] => 11119274
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/119274 | Barrier metal cap structure on copper lines and vias | Apr 28, 2005 | Abandoned |