Search

Pierre E Elisca

Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715
Total Applications
2631
Issued Applications
2140
Pending Applications
221
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14079801 [patent_doc_number] => 20190088788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Thin Film Transistor and Method of Fabricating the Same, Array Substrate and Display Device [patent_app_type] => utility [patent_app_number] => 16/050294 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050294
Thin film transistor and method of fabricating the same, array substrate and display device Jul 30, 2018 Issued
Array ( [id] => 14985187 [patent_doc_number] => 10446514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Combing bump structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/048357 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2730 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048357
Combing bump structure and manufacturing method thereof Jul 29, 2018 Issued
Array ( [id] => 13785669 [patent_doc_number] => 20190006373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => PREVENTING GATE-TO-CONTACT BRIDGING BY REDUCING CONTACT DIMENSIONS IN FINFET SRAM [patent_app_type] => utility [patent_app_number] => 16/046188 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046188 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046188
Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM Jul 25, 2018 Issued
Array ( [id] => 13419837 [patent_doc_number] => 20180261461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SALICIDE FORMATION USING A CAP LAYER [patent_app_type] => utility [patent_app_number] => 15/981665 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981665 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981665
SALICIDE FORMATION USING A CAP LAYER May 15, 2018 Pending
Array ( [id] => 18331957 [patent_doc_number] => 11637215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Pin/pin stacked photodetection film and photodetection display apparatus [patent_app_type] => utility [patent_app_number] => 16/611460 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5960 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16611460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/611460
Pin/pin stacked photodetection film and photodetection display apparatus May 14, 2018 Issued
Array ( [id] => 17863093 [patent_doc_number] => 11444255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Method of manufacturing display device, display device, display module, and electronic device [patent_app_type] => utility [patent_app_number] => 16/611503 [patent_app_country] => US [patent_app_date] => 2018-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 72 [patent_no_of_words] => 21410 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16611503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/611503
Method of manufacturing display device, display device, display module, and electronic device May 10, 2018 Issued
Array ( [id] => 13528315 [patent_doc_number] => 20180315700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SELF-ENCLOSED ASYMMETRIC INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/967256 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967256 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967256
SELF-ENCLOSED ASYMMETRIC INTERCONNECT STRUCTURES Apr 29, 2018 Abandoned
Array ( [id] => 18292382 [patent_doc_number] => 11621255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Optoelectronic component having an optical element with different inner surface regions [patent_app_type] => utility [patent_app_number] => 16/608356 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5202 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16608356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/608356
Optoelectronic component having an optical element with different inner surface regions Apr 24, 2018 Issued
Array ( [id] => 16796051 [patent_doc_number] => 20210125868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => CHIP PRODUCTION METHOD, AND, SILICON CHIP [patent_app_type] => utility [patent_app_number] => 16/605878 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605878 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/605878
Forming openings at intersection of cutting lines Feb 8, 2018 Issued
Array ( [id] => 12738865 [patent_doc_number] => 20180138122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 15/855510 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855510 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855510
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME Dec 26, 2017 Abandoned
Array ( [id] => 13559027 [patent_doc_number] => 20180331061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => INTEGRATED DEVICE COMPRISING BUMP ON EXPOSED REDISTRIBUTION INTERCONNECT [patent_app_type] => utility [patent_app_number] => 15/843865 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843865 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843865
INTEGRATED DEVICE COMPRISING BUMP ON EXPOSED REDISTRIBUTION INTERCONNECT Dec 14, 2017 Abandoned
Array ( [id] => 16578752 [patent_doc_number] => 20210013153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => DISPLAY SUBSTRATE ASSEMBLY AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/070271 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070271 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/070271
Display having an amorphous silicon light shield below a thin film transistor Dec 13, 2017 Issued
Array ( [id] => 16873755 [patent_doc_number] => 20210167222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/067297 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16067297 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/067297
Thin film transistor having a wire grid on a channel region and manufacturing method thereof, array substrate and manufacturing method thereof, and display panel Nov 16, 2017 Issued
Array ( [id] => 15699195 [patent_doc_number] => 10605768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Nanofluid sensor with real-time spatial sensing [patent_app_type] => utility [patent_app_number] => 15/671949 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6082 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671949 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/671949
Nanofluid sensor with real-time spatial sensing Aug 7, 2017 Issued
Array ( [id] => 15247531 [patent_doc_number] => 10509287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Color filter on array substrate having a photoresist plug contacting a liquid crystal layer [patent_app_type] => utility [patent_app_number] => 15/648631 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4372 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648631 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/648631
Color filter on array substrate having a photoresist plug contacting a liquid crystal layer Jul 12, 2017 Issued
Array ( [id] => 13785663 [patent_doc_number] => 20190006370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => PREVENTING GATE-TO-CONTACT BRIDGING BY REDUCING CONTACT DIMENSIONS IN FINFET SRAM [patent_app_type] => utility [patent_app_number] => 15/636832 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636832 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/636832
Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM Jun 28, 2017 Issued
Array ( [id] => 12154739 [patent_doc_number] => 20180026004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'BONDING WIRE, WIRE BONDING METHOD USING THE BONDING WIRE, AND ELECTRICAL CONNECTION PART OF SEMICONDUCTOR DEVICE USING THE BONDING WIRE' [patent_app_type] => utility [patent_app_number] => 15/616525 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616525
Bonding wire having a silver alloy core, wire bonding method using the bonding wire, and electrical connection part of semiconductor device using the bonding wire Jun 6, 2017 Issued
Array ( [id] => 13581855 [patent_doc_number] => 20180342476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLY WITH SURFACE-MOUNT DIE SUPPORT STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/603327 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603327
Semiconductor device assembly with surface-mount die support structures May 22, 2017 Issued
Array ( [id] => 13581853 [patent_doc_number] => 20180342475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/603175 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603175 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603175
Semiconductor device assembly with die support structures May 22, 2017 Issued
Array ( [id] => 13571137 [patent_doc_number] => 20180337116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE [patent_app_type] => utility [patent_app_number] => 15/598304 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598304
Semiconductor structure having bump on tilting upper corner surface May 16, 2017 Issued
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