Search

Pierre M. Vital

Supervisory Patent Examiner (ID: 2202, Phone: (571)272-4215 , Office: P/2162 )

Most Active Art Unit
2188
Art Unit(s)
2186, 2752, 2188, 2169, 2156, 2162, 2198
Total Applications
390
Issued Applications
296
Pending Applications
16
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5910525 [patent_doc_number] => 20020144061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Vector and scalar data cache for a vector multiprocessor' [patent_app_type] => new [patent_app_number] => 09/981380 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144061.pdf [firstpage_image] =>[orig_patent_app_number] => 09981380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/981380
Vector and scalar data cache for a vector multiprocessor Oct 15, 2001 Issued
Array ( [id] => 1161548 [patent_doc_number] => 06775754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Memory apparatus and memory access restricting method' [patent_app_type] => B2 [patent_app_number] => 09/967410 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4879 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775754.pdf [firstpage_image] =>[orig_patent_app_number] => 09967410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/967410
Memory apparatus and memory access restricting method Sep 27, 2001 Issued
Array ( [id] => 5876812 [patent_doc_number] => 20020049871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Method and system for virtual memory compression in an embedded system' [patent_app_type] => new [patent_app_number] => 09/960853 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8271 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20020049871.pdf [firstpage_image] =>[orig_patent_app_number] => 09960853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/960853
Method and system for virtual memory compression in an embedded system Sep 20, 2001 Issued
Array ( [id] => 782195 [patent_doc_number] => 06996663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-07 [patent_title] => 'Method and apparatus for performing address translation using a CAM' [patent_app_type] => utility [patent_app_number] => 09/951038 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2854 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996663.pdf [firstpage_image] =>[orig_patent_app_number] => 09951038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951038
Method and apparatus for performing address translation using a CAM Sep 11, 2001 Issued
Array ( [id] => 5890324 [patent_doc_number] => 20020013881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Dynamically-tunable memory controller' [patent_app_type] => new [patent_app_number] => 09/938161 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14965 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013881.pdf [firstpage_image] =>[orig_patent_app_number] => 09938161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938161
Dynamically-tunable memory controller Aug 22, 2001 Issued
Array ( [id] => 6689757 [patent_doc_number] => 20030033483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Cache architecture to reduce leakage power consumption' [patent_app_type] => new [patent_app_number] => 09/928671 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2110 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20030033483.pdf [firstpage_image] =>[orig_patent_app_number] => 09928671 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928671
Cache architecture to reduce leakage power consumption Aug 12, 2001 Abandoned
Array ( [id] => 6181372 [patent_doc_number] => 20020156991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Method and apparatus for 24-bit memory addressing in microcontrollers' [patent_app_type] => new [patent_app_number] => 09/924249 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7987 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20020156991.pdf [firstpage_image] =>[orig_patent_app_number] => 09924249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924249
Method and apparatus for 24-bit memory addressing in microcontrollers Aug 6, 2001 Issued
Array ( [id] => 1206869 [patent_doc_number] => 06721851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'System and method for preventing sector slipping in a storage area network' [patent_app_type] => B2 [patent_app_number] => 09/924228 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2762 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721851.pdf [firstpage_image] =>[orig_patent_app_number] => 09924228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924228
System and method for preventing sector slipping in a storage area network Aug 6, 2001 Issued
Array ( [id] => 1185837 [patent_doc_number] => 06745301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Microcontroller programmable method for accessing external memory in a page mode operation' [patent_app_type] => B2 [patent_app_number] => 09/924631 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3086 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745301.pdf [firstpage_image] =>[orig_patent_app_number] => 09924631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924631
Microcontroller programmable method for accessing external memory in a page mode operation Aug 6, 2001 Issued
Array ( [id] => 7613848 [patent_doc_number] => 06898683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Clock synchronized dynamic memory and clock synchronized integrated circuit' [patent_app_type] => utility [patent_app_number] => 09/922742 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 8682 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898683.pdf [firstpage_image] =>[orig_patent_app_number] => 09922742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922742
Clock synchronized dynamic memory and clock synchronized integrated circuit Aug 6, 2001 Issued
Array ( [id] => 1052605 [patent_doc_number] => 06862671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'System and method for optimizing establishment of mirrored data' [patent_app_type] => utility [patent_app_number] => 09/923155 [patent_app_country] => US [patent_app_date] => 2001-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3988 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862671.pdf [firstpage_image] =>[orig_patent_app_number] => 09923155 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923155
System and method for optimizing establishment of mirrored data Aug 5, 2001 Issued
Array ( [id] => 1248835 [patent_doc_number] => 06678791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'System and method for session-aware caching' [patent_app_type] => B1 [patent_app_number] => 09/923072 [patent_app_country] => US [patent_app_date] => 2001-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5179 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678791.pdf [firstpage_image] =>[orig_patent_app_number] => 09923072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923072
System and method for session-aware caching Aug 3, 2001 Issued
Array ( [id] => 1138985 [patent_doc_number] => 06789170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'System and method for customizing cached data' [patent_app_type] => B1 [patent_app_number] => 09/923103 [patent_app_country] => US [patent_app_date] => 2001-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7240 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789170.pdf [firstpage_image] =>[orig_patent_app_number] => 09923103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923103
System and method for customizing cached data Aug 3, 2001 Issued
Array ( [id] => 1143495 [patent_doc_number] => 06785769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Multi-version data caching' [patent_app_type] => B1 [patent_app_number] => 09/923073 [patent_app_country] => US [patent_app_date] => 2001-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5275 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785769.pdf [firstpage_image] =>[orig_patent_app_number] => 09923073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923073
Multi-version data caching Aug 3, 2001 Issued
Array ( [id] => 6717390 [patent_doc_number] => 20030028738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Methods and systems for efficiently managing persistent storage' [patent_app_type] => new [patent_app_number] => 09/921820 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028738.pdf [firstpage_image] =>[orig_patent_app_number] => 09921820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921820
Methods and systems for efficiently managing persistent storage Aug 2, 2001 Issued
Array ( [id] => 5937831 [patent_doc_number] => 20020062429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Storage system and method for data transfer between storage systems' [patent_app_type] => new [patent_app_number] => 09/922462 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3779 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20020062429.pdf [firstpage_image] =>[orig_patent_app_number] => 09922462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922462
Storage system and method for data transfer between storage systems Aug 2, 2001 Issued
Array ( [id] => 6717377 [patent_doc_number] => 20030028725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Redundant array of independent storage devices' [patent_app_type] => new [patent_app_number] => 09/922436 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6798 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028725.pdf [firstpage_image] =>[orig_patent_app_number] => 09922436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922436
Atomic resolution storage device configured as a redundant array of independent storage devices Aug 2, 2001 Issued
Array ( [id] => 6035544 [patent_doc_number] => 20020019912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Multi-port cache memory' [patent_app_type] => new [patent_app_number] => 09/919859 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8803 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019912.pdf [firstpage_image] =>[orig_patent_app_number] => 09919859 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919859
Multi-port cache memory Aug 1, 2001 Issued
Array ( [id] => 7628192 [patent_doc_number] => 06820168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Storage system and virtual private volume control method' [patent_app_type] => B2 [patent_app_number] => 09/918796 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8336 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820168.pdf [firstpage_image] =>[orig_patent_app_number] => 09918796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918796
Storage system and virtual private volume control method Jul 31, 2001 Issued
Array ( [id] => 6717375 [patent_doc_number] => 20030028723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Efficient data backup using a single side file' [patent_app_type] => new [patent_app_number] => 09/918713 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4901 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028723.pdf [firstpage_image] =>[orig_patent_app_number] => 09918713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918713
Efficient data backup using a single side file Jul 31, 2001 Issued
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