Search

Pierre M. Vital

Supervisory Patent Examiner (ID: 2202, Phone: (571)272-4215 , Office: P/2162 )

Most Active Art Unit
2188
Art Unit(s)
2186, 2752, 2188, 2169, 2156, 2162, 2198
Total Applications
390
Issued Applications
296
Pending Applications
16
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1240836 [patent_doc_number] => 06691203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Integrated controller to process both optical reads and optical writes of multiple optical media' [patent_app_type] => B1 [patent_app_number] => 09/652254 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 40 [patent_no_of_words] => 16014 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691203.pdf [firstpage_image] =>[orig_patent_app_number] => 09652254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652254
Integrated controller to process both optical reads and optical writes of multiple optical media Aug 29, 2000 Issued
Array ( [id] => 1200965 [patent_doc_number] => 06728835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Leaky cache mechanism' [patent_app_type] => B1 [patent_app_number] => 09/650730 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3233 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728835.pdf [firstpage_image] =>[orig_patent_app_number] => 09650730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650730
Leaky cache mechanism Aug 29, 2000 Issued
Array ( [id] => 1169761 [patent_doc_number] => 06763443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'System and method for using a synchronous memory device with an asynchronous memory controller' [patent_app_type] => B1 [patent_app_number] => 09/651273 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11671 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763443.pdf [firstpage_image] =>[orig_patent_app_number] => 09651273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651273
System and method for using a synchronous memory device with an asynchronous memory controller Aug 29, 2000 Issued
Array ( [id] => 1166002 [patent_doc_number] => 06772300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method and apparatus for managing out of order memory transactions' [patent_app_type] => B1 [patent_app_number] => 09/651437 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3188 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772300.pdf [firstpage_image] =>[orig_patent_app_number] => 09651437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651437
Method and apparatus for managing out of order memory transactions Aug 29, 2000 Issued
Array ( [id] => 1567378 [patent_doc_number] => 06438659 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Directory based cache coherency system supporting multiple instruction processor and input/output caches' [patent_app_type] => B1 [patent_app_number] => 09/645233 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 15334 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438659.pdf [firstpage_image] =>[orig_patent_app_number] => 09645233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645233
Directory based cache coherency system supporting multiple instruction processor and input/output caches Aug 23, 2000 Issued
Array ( [id] => 1214364 [patent_doc_number] => 06715036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method, system, and data structures for transferring blocks of data from a storage device to a requesting application' [patent_app_type] => B1 [patent_app_number] => 09/628394 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7321 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715036.pdf [firstpage_image] =>[orig_patent_app_number] => 09628394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628394
Method, system, and data structures for transferring blocks of data from a storage device to a requesting application Jul 31, 2000 Issued
Array ( [id] => 1366457 [patent_doc_number] => 06584544 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Method and apparatus for preparing a disk for use in a disk array' [patent_app_type] => B1 [patent_app_number] => 09/614820 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4144 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584544.pdf [firstpage_image] =>[orig_patent_app_number] => 09614820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614820
Method and apparatus for preparing a disk for use in a disk array Jul 11, 2000 Issued
Array ( [id] => 7633089 [patent_doc_number] => 06658531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method and apparatus for accessing graphics cache memory' [patent_app_type] => B1 [patent_app_number] => 09/614931 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6893 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658531.pdf [firstpage_image] =>[orig_patent_app_number] => 09614931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614931
Method and apparatus for accessing graphics cache memory Jul 11, 2000 Issued
Array ( [id] => 1206854 [patent_doc_number] => 06721843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible' [patent_app_type] => B1 [patent_app_number] => 09/611676 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10687 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721843.pdf [firstpage_image] =>[orig_patent_app_number] => 09611676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/611676
Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible Jul 6, 2000 Issued
Array ( [id] => 1218192 [patent_doc_number] => 06711661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method and apparatus for performing hierarchical address translation' [patent_app_type] => B1 [patent_app_number] => 09/606995 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5090 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711661.pdf [firstpage_image] =>[orig_patent_app_number] => 09606995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606995
Method and apparatus for performing hierarchical address translation Jun 28, 2000 Issued
Array ( [id] => 1289011 [patent_doc_number] => 06647462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Apparatus and a method for providing decoded information' [patent_app_type] => B1 [patent_app_number] => 09/607564 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4935 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647462.pdf [firstpage_image] =>[orig_patent_app_number] => 09607564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607564
Apparatus and a method for providing decoded information Jun 28, 2000 Issued
Array ( [id] => 1573773 [patent_doc_number] => 06499092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Method and apparatus for performing access censorship in a data processing system' [patent_app_type] => B1 [patent_app_number] => 09/593216 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3835 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499092.pdf [firstpage_image] =>[orig_patent_app_number] => 09593216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593216
Method and apparatus for performing access censorship in a data processing system Jun 13, 2000 Issued
Array ( [id] => 1271887 [patent_doc_number] => 06662283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Secure memory management method' [patent_app_type] => B1 [patent_app_number] => 09/567062 [patent_app_country] => US [patent_app_date] => 2000-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4714 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662283.pdf [firstpage_image] =>[orig_patent_app_number] => 09567062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567062
Secure memory management method May 7, 2000 Issued
09/560929 Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent Apr 29, 2000 Abandoned
Array ( [id] => 1519646 [patent_doc_number] => 06421760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Disk array controller, and components thereof, for use with ATA disk drives' [patent_app_type] => B1 [patent_app_number] => 09/558524 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12113 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421760.pdf [firstpage_image] =>[orig_patent_app_number] => 09558524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/558524
Disk array controller, and components thereof, for use with ATA disk drives Apr 25, 2000 Issued
Array ( [id] => 1046310 [patent_doc_number] => 06868471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Memory address space extension device and storage medium storing therein program thereof' [patent_app_type] => utility [patent_app_number] => 09/551799 [patent_app_country] => US [patent_app_date] => 2000-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6058 [patent_no_of_claims] => 124 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868471.pdf [firstpage_image] =>[orig_patent_app_number] => 09551799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/551799
Memory address space extension device and storage medium storing therein program thereof Apr 17, 2000 Issued
09/547034 Method and apparatus for wire-speed application layer classification of data packets Apr 10, 2000 Abandoned
Array ( [id] => 1248865 [patent_doc_number] => 06678804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Apparatus and method for memory access control' [patent_app_type] => B1 [patent_app_number] => 09/545079 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10900 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678804.pdf [firstpage_image] =>[orig_patent_app_number] => 09545079 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545079
Apparatus and method for memory access control Apr 6, 2000 Issued
Array ( [id] => 1234266 [patent_doc_number] => 06697917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Processor having cache purge controller' [patent_app_type] => B1 [patent_app_number] => 09/537356 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2165 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697917.pdf [firstpage_image] =>[orig_patent_app_number] => 09537356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537356
Processor having cache purge controller Mar 28, 2000 Issued
Array ( [id] => 1356912 [patent_doc_number] => 06591333 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method for completing incomplete recording on an optical disk' [patent_app_type] => B1 [patent_app_number] => 09/538122 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2373 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591333.pdf [firstpage_image] =>[orig_patent_app_number] => 09538122 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538122
Method for completing incomplete recording on an optical disk Mar 27, 2000 Issued
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