Pierre M. Vital

Array ( [id] => 1592363 [patent_doc_number] => 06360308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Buffer controller' [patent_app_type] => B1 [patent_app_number] => 09/163835 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5446 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360308.pdf [firstpage_image] =>[orig_patent_app_number] => 09163835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1361150 [patent_doc_number] => 06587912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method and apparatus for implementing multiple memory buses on a memory module' [patent_app_type] => B2 [patent_app_number] => 09/163860 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5859 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587912.pdf [firstpage_image] =>[orig_patent_app_number] => 09163860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424718 [patent_doc_number] => 06230235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Address lookup DRAM aging' [patent_app_type] => 1 [patent_app_number] => 9/163074 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 18298 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230235.pdf [firstpage_image] =>[orig_patent_app_number] => 163074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4403976 [patent_doc_number] => 06263410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Apparatus and method for asynchronous dual port FIFO' [patent_app_type] => 1 [patent_app_number] => 9/153679 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3988 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263410.pdf [firstpage_image] =>[orig_patent_app_number] => 153679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6908570 [patent_doc_number] => 20010011337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'PROGRAMMABLE MULTIPLE SEQUENTIAL SECTOR LOCKING FOR SEMICONDUTOR MEMORIES' [patent_app_type] => new [patent_app_number] => 09/153375 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 990 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011337.pdf [firstpage_image] =>[orig_patent_app_number] => 09153375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1471956 [patent_doc_number] => 06460121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method for providing an atomic memory read using a compare-exchange instruction primitive' [patent_app_type] => B1 [patent_app_number] => 09/152888 [patent_app_country] => US [patent_app_date] => 1998-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460121.pdf [firstpage_image] =>[orig_patent_app_number] => 09152888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466184 [patent_doc_number] => 06393521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Information processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/140280 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5293 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393521.pdf [firstpage_image] =>[orig_patent_app_number] => 09140280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4337251 [patent_doc_number] => 06249854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Data reading method and apparatus for a disk drive storage device' [patent_app_type] => 1 [patent_app_number] => 9/140616 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5148 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249854.pdf [firstpage_image] =>[orig_patent_app_number] => 140616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4400280 [patent_doc_number] => 06304947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Optimized memory organization in a multi-channel architecture' [patent_app_type] => 1 [patent_app_number] => 9/140427 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4644 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304947.pdf [firstpage_image] =>[orig_patent_app_number] => 140427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4391566 [patent_doc_number] => 06289416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Disk drive device and a method for controlling the same' [patent_app_type] => 1 [patent_app_number] => 9/139933 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289416.pdf [firstpage_image] =>[orig_patent_app_number] => 139933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1539218 [patent_doc_number] => 06412053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'System method and apparatus for providing linearly scalable dynamic memory management in a multiprocessing system' [patent_app_type] => B1 [patent_app_number] => 09/140210 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4335 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412053.pdf [firstpage_image] =>[orig_patent_app_number] => 09140210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1513226 [patent_doc_number] => 06442644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Memory system having synchronous-link DRAM (SLDRAM) devices and controller' [patent_app_type] => B1 [patent_app_number] => 09/132158 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 30081 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442644.pdf [firstpage_image] =>[orig_patent_app_number] => 09132158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1434040 [patent_doc_number] => 06341330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method and system for caching a selected viewing angle in a DVD environment' [patent_app_type] => B1 [patent_app_number] => 09/122812 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4716 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341330.pdf [firstpage_image] =>[orig_patent_app_number] => 09122812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4273573 [patent_doc_number] => 06209066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method and apparatus for memory allocation in a multi-threaded virtual machine' [patent_app_type] => 1 [patent_app_number] => 9/108047 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15033 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209066.pdf [firstpage_image] =>[orig_patent_app_number] => 108047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4371060 [patent_doc_number] => 06216202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method and apparatus for managing virtual storage devices in a storage system' [patent_app_type] => 1 [patent_app_number] => 9/107617 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6998 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216202.pdf [firstpage_image] =>[orig_patent_app_number] => 107617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7610026 [patent_doc_number] => 06842833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Computer system and method for transferring data between multiple peer-level storage units' [patent_app_type] => utility [patent_app_number] => 09/107539 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3260 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842833.pdf [firstpage_image] =>[orig_patent_app_number] => 09107539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1595868 [patent_doc_number] => 06484234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method and apparatus for efficiently destaging data from a cache to two or more non-contiguous storage locations' [patent_app_type] => B1 [patent_app_number] => 09/107792 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 14648 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484234.pdf [firstpage_image] =>[orig_patent_app_number] => 09107792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602255 [patent_doc_number] => 06493802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method and apparatus for performing speculative memory fills into a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/099396 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4681 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493802.pdf [firstpage_image] =>[orig_patent_app_number] => 09099396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4316473 [patent_doc_number] => 06199153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements' [patent_app_type] => 1 [patent_app_number] => 9/099383 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4007 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199153.pdf [firstpage_image] =>[orig_patent_app_number] => 099383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6143549 [patent_doc_number] => 20020002659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'SYSTEM AND METHOD FOR IMPROVING DIRECTORY LOOKUP SPEED' [patent_app_type] => new [patent_app_number] => 09/087094 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3095 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20020002659.pdf [firstpage_image] =>[orig_patent_app_number] => 09087094 [rel_patent_id] =>[rel_patent_doc_number] =>)