Search

Pierre M. Vital

Supervisory Patent Examiner (ID: 2202, Phone: (571)272-4215 , Office: P/2162 )

Most Active Art Unit
2188
Art Unit(s)
2186, 2752, 2188, 2169, 2156, 2162, 2198
Total Applications
390
Issued Applications
296
Pending Applications
16
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1466656 [patent_doc_number] => 06351789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Built-in self-test circuit and method for validating an associative data array' [patent_app_type] => B1 [patent_app_number] => 09/086866 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10904 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351789.pdf [firstpage_image] =>[orig_patent_app_number] => 09086866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086866
Built-in self-test circuit and method for validating an associative data array May 28, 1998 Issued
Array ( [id] => 4333099 [patent_doc_number] => 06332172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method and system for virtual memory compression in an embedded system' [patent_app_type] => 1 [patent_app_number] => 9/087382 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8233 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332172.pdf [firstpage_image] =>[orig_patent_app_number] => 087382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087382
Method and system for virtual memory compression in an embedded system May 28, 1998 Issued
Array ( [id] => 1572421 [patent_doc_number] => 06378057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Data processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/085434 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9514 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378057.pdf [firstpage_image] =>[orig_patent_app_number] => 09085434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085434
Data processing apparatus May 26, 1998 Issued
Array ( [id] => 4424128 [patent_doc_number] => 06301644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method for managing defect sectors of information storage medium, and apparatus for use with the method' [patent_app_type] => 1 [patent_app_number] => 9/069034 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6873 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301644.pdf [firstpage_image] =>[orig_patent_app_number] => 069034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069034
Method for managing defect sectors of information storage medium, and apparatus for use with the method Apr 26, 1998 Issued
Array ( [id] => 1572463 [patent_doc_number] => 06378065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Apparatus with context switching capability' [patent_app_type] => B1 [patent_app_number] => 09/069030 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7241 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378065.pdf [firstpage_image] =>[orig_patent_app_number] => 09069030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069030
Apparatus with context switching capability Apr 26, 1998 Issued
Array ( [id] => 1466221 [patent_doc_number] => 06393530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Paging method for DSP' [patent_app_type] => B1 [patent_app_number] => 09/062030 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 19310 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393530.pdf [firstpage_image] =>[orig_patent_app_number] => 09062030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062030
Paging method for DSP Apr 16, 1998 Issued
Array ( [id] => 1381372 [patent_doc_number] => 06574698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Method and system for accessing a cache memory within a data processing system' [patent_app_type] => B1 [patent_app_number] => 09/062002 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3252 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574698.pdf [firstpage_image] =>[orig_patent_app_number] => 09062002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062002
Method and system for accessing a cache memory within a data processing system Apr 16, 1998 Issued
Array ( [id] => 1248859 [patent_doc_number] => 06678801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'DSP with distributed RAM structure' [patent_app_type] => B1 [patent_app_number] => 09/062146 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 19563 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678801.pdf [firstpage_image] =>[orig_patent_app_number] => 09062146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062146
DSP with distributed RAM structure Apr 16, 1998 Issued
Array ( [id] => 4373721 [patent_doc_number] => 06202130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Data processing system for processing vector data and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/061975 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4488 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202130.pdf [firstpage_image] =>[orig_patent_app_number] => 061975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061975
Data processing system for processing vector data and method therefor Apr 16, 1998 Issued
Array ( [id] => 4109935 [patent_doc_number] => 06134630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'High-performance bus architecture for disk array system' [patent_app_type] => 1 [patent_app_number] => 9/034247 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12770 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134630.pdf [firstpage_image] =>[orig_patent_app_number] => 034247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034247
High-performance bus architecture for disk array system Mar 3, 1998 Issued
Array ( [id] => 4399213 [patent_doc_number] => 06295581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method and apparatus for assuring cache coherency' [patent_app_type] => 1 [patent_app_number] => 9/026942 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6463 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295581.pdf [firstpage_image] =>[orig_patent_app_number] => 026942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026942
Method and apparatus for assuring cache coherency Feb 19, 1998 Issued
Array ( [id] => 4177835 [patent_doc_number] => 06108761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method of and apparatus for saving time performing certain transfer instructions' [patent_app_type] => 1 [patent_app_number] => 9/026840 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3976 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108761.pdf [firstpage_image] =>[orig_patent_app_number] => 026840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026840
Method of and apparatus for saving time performing certain transfer instructions Feb 19, 1998 Issued
Array ( [id] => 4257076 [patent_doc_number] => 06081881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method of and apparatus for speeding up the execution of normal extended mode transfer instructions' [patent_app_type] => 1 [patent_app_number] => 9/026935 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2966 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081881.pdf [firstpage_image] =>[orig_patent_app_number] => 026935 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026935
Method of and apparatus for speeding up the execution of normal extended mode transfer instructions Feb 19, 1998 Issued
Array ( [id] => 1553777 [patent_doc_number] => 06347361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Cache coherency protocols with posted operations' [patent_app_type] => B1 [patent_app_number] => 09/024587 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8605 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347361.pdf [firstpage_image] =>[orig_patent_app_number] => 09024587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024587
Cache coherency protocols with posted operations Feb 16, 1998 Issued
Array ( [id] => 1495326 [patent_doc_number] => 06418514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Removal of posted operations from cache operations queue' [patent_app_type] => B1 [patent_app_number] => 09/024382 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418514.pdf [firstpage_image] =>[orig_patent_app_number] => 09024382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024382
Removal of posted operations from cache operations queue Feb 16, 1998 Issued
Array ( [id] => 1481709 [patent_doc_number] => 06345340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Cache coherency protocol with ambiguous state for posted operations' [patent_app_type] => B1 [patent_app_number] => 09/024608 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8594 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345340.pdf [firstpage_image] =>[orig_patent_app_number] => 09024608 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024608
Cache coherency protocol with ambiguous state for posted operations Feb 16, 1998 Issued
Array ( [id] => 4257674 [patent_doc_number] => 06145062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Selective conflict write flush' [patent_app_type] => 1 [patent_app_number] => 9/013775 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3211 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145062.pdf [firstpage_image] =>[orig_patent_app_number] => 013775 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013775
Selective conflict write flush Jan 25, 1998 Issued
Array ( [id] => 1495340 [patent_doc_number] => 06418517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Optimized function execution for a multiprocessor computer system' [patent_app_type] => B1 [patent_app_number] => 09/001570 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13510 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418517.pdf [firstpage_image] =>[orig_patent_app_number] => 09001570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001570
Optimized function execution for a multiprocessor computer system Dec 30, 1997 Issued
Array ( [id] => 4412390 [patent_doc_number] => 06298426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Controller configurable for use with multiple memory organizations' [patent_app_type] => 1 [patent_app_number] => 9/002293 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4270 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298426.pdf [firstpage_image] =>[orig_patent_app_number] => 002293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002293
Controller configurable for use with multiple memory organizations Dec 30, 1997 Issued
Array ( [id] => 6973976 [patent_doc_number] => 20010003836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-14 [patent_title] => 'PLURAL BUS DATA STORAGE SYSTEM' [patent_app_type] => new-utility [patent_app_number] => 08/997215 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3878 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003836.pdf [firstpage_image] =>[orig_patent_app_number] => 08997215 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997215
Plural bus data storage system Dec 22, 1997 Issued
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