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Pierre M. Vital

Supervisory Patent Examiner (ID: 2202, Phone: (571)272-4215 , Office: P/2162 )

Most Active Art Unit
2188
Art Unit(s)
2186, 2752, 2188, 2169, 2156, 2162, 2198
Total Applications
390
Issued Applications
296
Pending Applications
16
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4257360 [patent_doc_number] => 06145042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Timing protocol for a data storage system' [patent_app_type] => 1 [patent_app_number] => 8/996809 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 2 [patent_no_of_words] => 6025 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145042.pdf [firstpage_image] =>[orig_patent_app_number] => 996809 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996809
Timing protocol for a data storage system Dec 22, 1997 Issued
Array ( [id] => 7638640 [patent_doc_number] => 06397281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Bus arbitration system' [patent_app_type] => B1 [patent_app_number] => 08/996807 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3766 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397281.pdf [firstpage_image] =>[orig_patent_app_number] => 08996807 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996807
Bus arbitration system Dec 22, 1997 Issued
Array ( [id] => 4373672 [patent_doc_number] => 06202127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Apparatus for spatial and temporal sampling in a computer memory system' [patent_app_type] => 1 [patent_app_number] => 8/979822 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7543 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202127.pdf [firstpage_image] =>[orig_patent_app_number] => 979822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979822
Apparatus for spatial and temporal sampling in a computer memory system Nov 25, 1997 Issued
Array ( [id] => 1526281 [patent_doc_number] => 06353834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Log based data architecture for a transactional message queuing system' [patent_app_type] => B1 [patent_app_number] => 08/963188 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6211 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353834.pdf [firstpage_image] =>[orig_patent_app_number] => 08963188 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963188
Log based data architecture for a transactional message queuing system Nov 2, 1997 Issued
Array ( [id] => 4379696 [patent_doc_number] => 06192457 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method for implementing a graphic address remapping table as a virtual register file in system memory' [patent_app_type] => 1 [patent_app_number] => 8/887868 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3800 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192457.pdf [firstpage_image] =>[orig_patent_app_number] => 887868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/887868
Method for implementing a graphic address remapping table as a virtual register file in system memory Jul 1, 1997 Issued
Array ( [id] => 1395609 [patent_doc_number] => 06567903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Data storage system having master/slave addressable memories' [patent_app_type] => B1 [patent_app_number] => 08/701917 [patent_app_country] => US [patent_app_date] => 1996-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 8313 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567903.pdf [firstpage_image] =>[orig_patent_app_number] => 08701917 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701917
Data storage system having master/slave addressable memories Aug 22, 1996 Issued
Array ( [id] => 1553792 [patent_doc_number] => 06347365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Data storage system having an memory responsive to clock pulses produced on a bus and clock pulses produced by an internal clock' [patent_app_type] => B1 [patent_app_number] => 08/701981 [patent_app_country] => US [patent_app_date] => 1996-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 8318 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347365.pdf [firstpage_image] =>[orig_patent_app_number] => 08701981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701981
Data storage system having an memory responsive to clock pulses produced on a bus and clock pulses produced by an internal clock Aug 22, 1996 Issued
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