Search

Pierre Miche Bataille

Examiner (ID: 16376)

Most Active Art Unit
2136
Art Unit(s)
2186, 2136, 2752
Total Applications
1964
Issued Applications
1749
Pending Applications
106
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16826256 [patent_doc_number] => 20210141549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => MEMORY SYSTEM AND SOC INCLUDING LINEAR ADDRESS REMAPPING LOGIC [patent_app_type] => utility [patent_app_number] => 17/155503 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155503 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155503
Memory system and SOC including linear address remapping logic Jan 21, 2021 Issued
Array ( [id] => 17737739 [patent_doc_number] => 20220223201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => Caching Techniques for Deep Learning Accelerator [patent_app_type] => utility [patent_app_number] => 17/146314 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146314
Caching techniques for deep learning accelerator Jan 10, 2021 Issued
Array ( [id] => 18577583 [patent_doc_number] => 11734115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Method and system for facilitating write latency reduction in a queue depth of one scenario [patent_app_type] => utility [patent_app_number] => 17/135404 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6433 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135404
Method and system for facilitating write latency reduction in a queue depth of one scenario Dec 27, 2020 Issued
Array ( [id] => 16849080 [patent_doc_number] => 20210149825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => FINE-GRAINED STACK PROTECTION USING CRYPTOGRAPHIC COMPUTING [patent_app_type] => utility [patent_app_number] => 17/134406 [patent_app_country] => US [patent_app_date] => 2020-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134406
Fine-grained stack protection using cryptographic computing Dec 25, 2020 Issued
Array ( [id] => 19212626 [patent_doc_number] => 12001689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Transparently attached flash memory security [patent_app_type] => utility [patent_app_number] => 17/133115 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133115
Transparently attached flash memory security Dec 22, 2020 Issued
Array ( [id] => 16903135 [patent_doc_number] => 20210182051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => CHIP HAVING MEMORY [patent_app_type] => utility [patent_app_number] => 17/118000 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118000
Chip having memory Dec 9, 2020 Issued
Array ( [id] => 17659337 [patent_doc_number] => 20220179802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => CACHE MANAGEMENT USING MULTIPLE CACHE MEMORIES AND FAVORED VOLUMES WITH MULTIPLE RESIDENCY TIME MULTIPLIERS [patent_app_type] => utility [patent_app_number] => 17/115008 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115008
Cache management using multiple cache memories and favored volumes with multiple residency time multipliers Dec 7, 2020 Issued
Array ( [id] => 18430301 [patent_doc_number] => 11675519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Techniques for facilitating processing checkpoints between computing devices [patent_app_type] => utility [patent_app_number] => 17/109077 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109077
Techniques for facilitating processing checkpoints between computing devices Nov 30, 2020 Issued
Array ( [id] => 16715373 [patent_doc_number] => 20210082520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => PROCESSOR IN NON-VOLATILE STORAGE MEMORY [patent_app_type] => utility [patent_app_number] => 17/103695 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103695
Processor in non-volatile storage memory Nov 23, 2020 Issued
Array ( [id] => 17507565 [patent_doc_number] => 20220100668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => METHOD AND APPARATUS FOR MONITORING MEMORY ACCESS TRAFFIC [patent_app_type] => utility [patent_app_number] => 17/094989 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094989
Method and apparatus for monitoring memory access traffic Nov 10, 2020 Issued
Array ( [id] => 16675765 [patent_doc_number] => 20210064531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SOFTWARE-DEFINED COHERENT CACHING OF POOLED MEMORY [patent_app_type] => utility [patent_app_number] => 17/092803 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092803
Software-defined coherent caching of pooled memory Nov 8, 2020 Issued
Array ( [id] => 17877238 [patent_doc_number] => 11449251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Storage control device and non-transitory computer-readable storage medium for storing control program [patent_app_type] => utility [patent_app_number] => 17/078142 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5443 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078142 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/078142
Storage control device and non-transitory computer-readable storage medium for storing control program Oct 22, 2020 Issued
Array ( [id] => 17565012 [patent_doc_number] => 20220129161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => SYSTEM AND METHOD TO USE DICTIONARIES IN LZ4 BLOCK FORMAT COMPRESSION [patent_app_type] => utility [patent_app_number] => 17/077885 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077885
System and method to use dictionaries in LZ4 block format compression Oct 21, 2020 Issued
Array ( [id] => 18446061 [patent_doc_number] => 11681632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Techniques for storing data and tags in different memory arrays [patent_app_type] => utility [patent_app_number] => 17/064342 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 21666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/064342
Techniques for storing data and tags in different memory arrays Oct 5, 2020 Issued
Array ( [id] => 17245625 [patent_doc_number] => 20210365369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/060157 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060157
Storage device for translating address and operating method thereof Sep 30, 2020 Issued
Array ( [id] => 17507575 [patent_doc_number] => 20220100678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => DUMMY DATA REMOVAL IN AN AUTHENTICATED ENCRYPTION WITH ASSOCIATED DATA CRYPTOGRAPHIC SCHEME [patent_app_type] => utility [patent_app_number] => 16/948691 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948691
Dummy data removal in an authenticated encryption with associated data cryptographic scheme Sep 28, 2020 Issued
Array ( [id] => 17507574 [patent_doc_number] => 20220100677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => MANAGING A LEAST-RECENTLY-USED DATA CACHE WITH A PERSISTENT BODY [patent_app_type] => utility [patent_app_number] => 17/036108 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036108
Managing a least-recently-used data cache with a persistent body Sep 28, 2020 Issued
Array ( [id] => 16764096 [patent_doc_number] => 20210109677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => METHOD AND SYSTEM FOR OFFLOADING LOOKUP OPERATION TO NAND OFFLOAD APPARATUS [patent_app_type] => utility [patent_app_number] => 17/036872 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036872
Method and system for offloading lookup operation to NAND offload apparatus Sep 28, 2020 Issued
Array ( [id] => 17484487 [patent_doc_number] => 20220091991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => MECHANISM TO EFFICIENTLY RINSE MEMORY-SIDE CACHE OF DIRTY DATA [patent_app_type] => utility [patent_app_number] => 17/031834 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031834 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031834
Mechanism to efficiently rinse memory-side cache of dirty data Sep 23, 2020 Issued
Array ( [id] => 16559020 [patent_doc_number] => 20210004169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/028087 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028087
Memory system Sep 21, 2020 Issued
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