Pierre Miche Bataille

Array ( [id] => 18400980 [patent_doc_number] => 11663118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Address vectors for data storage elements [patent_app_type] => utility [patent_app_number] => 17/198003 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18189438 [patent_doc_number] => 11580023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Information processing apparatus, computer-readable recording medium having stored therein memory control program, and computer-readable recording medium having stored therein information processing program [patent_app_type] => utility [patent_app_number] => 17/189436 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14484 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17475970 [patent_doc_number] => 20220083474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => WRITE-BACK CACHE DEVICE [patent_app_type] => utility [patent_app_number] => 17/186192 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18291368 [patent_doc_number] => 11620238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-04 [patent_title] => Hardware blinding of memory access with epoch transitions [patent_app_type] => utility [patent_app_number] => 17/185752 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 11481 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18414911 [patent_doc_number] => 11669453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Data prefetching method and apparatus [patent_app_type] => utility [patent_app_number] => 17/182401 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 23062 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17817318 [patent_doc_number] => 11422930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Controller, memory system and data processing system [patent_app_type] => utility [patent_app_number] => 17/181328 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18949981 [patent_doc_number] => 11893277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Data storage device managing low endurance semiconductor memory write cache [patent_app_type] => utility [patent_app_number] => 17/180782 [patent_app_country] => US [patent_app_date] => 2021-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4033 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16872111 [patent_doc_number] => 20210165578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => Operating Parameters for Non-Volatile Memory Devices [patent_app_type] => utility [patent_app_number] => 17/177102 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17177102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16826256 [patent_doc_number] => 20210141549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => MEMORY SYSTEM AND SOC INCLUDING LINEAR ADDRESS REMAPPING LOGIC [patent_app_type] => utility [patent_app_number] => 17/155503 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17737739 [patent_doc_number] => 20220223201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => Caching Techniques for Deep Learning Accelerator [patent_app_type] => utility [patent_app_number] => 17/146314 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18577583 [patent_doc_number] => 11734115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Method and system for facilitating write latency reduction in a queue depth of one scenario [patent_app_type] => utility [patent_app_number] => 17/135404 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6433 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16849080 [patent_doc_number] => 20210149825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => FINE-GRAINED STACK PROTECTION USING CRYPTOGRAPHIC COMPUTING [patent_app_type] => utility [patent_app_number] => 17/134406 [patent_app_country] => US [patent_app_date] => 2020-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19212626 [patent_doc_number] => 12001689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Transparently attached flash memory security [patent_app_type] => utility [patent_app_number] => 17/133115 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16903135 [patent_doc_number] => 20210182051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => CHIP HAVING MEMORY [patent_app_type] => utility [patent_app_number] => 17/118000 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17659337 [patent_doc_number] => 20220179802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => CACHE MANAGEMENT USING MULTIPLE CACHE MEMORIES AND FAVORED VOLUMES WITH MULTIPLE RESIDENCY TIME MULTIPLIERS [patent_app_type] => utility [patent_app_number] => 17/115008 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18430301 [patent_doc_number] => 11675519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Techniques for facilitating processing checkpoints between computing devices [patent_app_type] => utility [patent_app_number] => 17/109077 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16715373 [patent_doc_number] => 20210082520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => PROCESSOR IN NON-VOLATILE STORAGE MEMORY [patent_app_type] => utility [patent_app_number] => 17/103695 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17507565 [patent_doc_number] => 20220100668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => METHOD AND APPARATUS FOR MONITORING MEMORY ACCESS TRAFFIC [patent_app_type] => utility [patent_app_number] => 17/094989 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16675765 [patent_doc_number] => 20210064531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SOFTWARE-DEFINED COHERENT CACHING OF POOLED MEMORY [patent_app_type] => utility [patent_app_number] => 17/092803 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17877238 [patent_doc_number] => 11449251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Storage control device and non-transitory computer-readable storage medium for storing control program [patent_app_type] => utility [patent_app_number] => 17/078142 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5443 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078142 [rel_patent_id] =>[rel_patent_doc_number] =>)