Search

Pierre Miche Bataille

Examiner (ID: 4053, Phone: (571)272-4178 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2136, 2138, 2186, 2752
Total Applications
1979
Issued Applications
1761
Pending Applications
108
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19530350 [patent_doc_number] => 20240354252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => CACHE MEMORY DEVICE AND METHOD FOR IMPLEMENTING CACHE SCHEDULING USING SAME [patent_app_type] => utility [patent_app_number] => 18/634662 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634662
Cache memory device and method for implementing cache scheduling using same Apr 11, 2024 Issued
Array ( [id] => 20234413 [patent_doc_number] => 20250291732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => DATA TRANSFER TECHNIQUE [patent_app_type] => utility [patent_app_number] => 18/634643 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 51667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634643
DATA TRANSFER TECHNIQUE Apr 11, 2024 Pending
Array ( [id] => 19514259 [patent_doc_number] => 20240345945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => CALCULATION PROCESSING APPARATUS AND CALCULATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/633240 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633240 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633240
CALCULATION PROCESSING APPARATUS AND CALCULATION PROCESSING METHOD Apr 10, 2024 Issued
Array ( [id] => 19334421 [patent_doc_number] => 20240248851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY [patent_app_type] => utility [patent_app_number] => 18/624301 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624301
Processor-based system for allocating cache lines to a higher-level cache memory Apr 1, 2024 Issued
Array ( [id] => 20304184 [patent_doc_number] => 12450172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Reducing set of policies with two or more hyper-dimensions [patent_app_type] => utility [patent_app_number] => 18/623103 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 19736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623103 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623103
Reducing set of policies with two or more hyper-dimensions Mar 31, 2024 Issued
Array ( [id] => 20304183 [patent_doc_number] => 12450171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Cache replacement system [patent_app_type] => utility [patent_app_number] => 18/623099 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 19345 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623099
Cache replacement system Mar 31, 2024 Issued
Array ( [id] => 19303038 [patent_doc_number] => 20240231617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL [patent_app_type] => utility [patent_app_number] => 18/612028 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612028
Memory device programming technique for increased bits per cell Mar 20, 2024 Issued
Array ( [id] => 19419842 [patent_doc_number] => 20240295965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MNAND FIELD TO PREDICT DEVICE PERFORMANCE [patent_app_type] => utility [patent_app_number] => 18/590721 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590721 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590721
MNAND field to predict device performance Feb 27, 2024 Issued
Array ( [id] => 19405755 [patent_doc_number] => 20240289266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => APPARATUSES AND METHODS FOR SETTINGS FOR ADJUSTABLE WRITE TIMING [patent_app_type] => utility [patent_app_number] => 18/441775 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441775 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441775
Apparatuses and methods for settings for adjustable write timing Feb 13, 2024 Issued
Array ( [id] => 19391513 [patent_doc_number] => 20240281383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => BUFFER EXPANSION FOR RANDOM WRITE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/431544 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431544
Buffer expansion for random write operations Feb 1, 2024 Issued
Array ( [id] => 19189732 [patent_doc_number] => 20240168645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => METHODS AND SYSTEMS FOR LIMITING DATA TRAFFIC WHILE PROCESSING COMPUTER SYSTEM OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/422162 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422162
Methods and systems for limiting data traffic while processing computer system operations Jan 24, 2024 Issued
Array ( [id] => 20228376 [patent_doc_number] => 12417027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Optimizing usage of multiple write paths on multi-tenant storage devices [patent_app_type] => utility [patent_app_number] => 18/420014 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420014 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420014
Optimizing usage of multiple write paths on multi-tenant storage devices Jan 22, 2024 Issued
Array ( [id] => 20095145 [patent_doc_number] => 20250225081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => PRIORITY-BASED CACHE EVICTION POLICY GOVERNED BY LATENCY CRITICAL CENTRAL PROCESSING UNIT (CPU) CORES [patent_app_type] => utility [patent_app_number] => 18/408322 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408322
Priority-based cache eviction policy governed by latency critical central processing unit (CPU) cores Jan 8, 2024 Issued
Array ( [id] => 19197753 [patent_doc_number] => 11994991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-28 [patent_title] => Cache memory device and method for implementing cache scheduling using same [patent_app_type] => utility [patent_app_number] => 18/508840 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7329 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508840
Cache memory device and method for implementing cache scheduling using same Nov 13, 2023 Issued
Array ( [id] => 20374157 [patent_doc_number] => 12481592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => System and method for tracing instruction cache misses [patent_app_type] => utility [patent_app_number] => 18/504468 [patent_app_country] => US [patent_app_date] => 2023-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3479 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/504468
System and method for tracing instruction cache misses Nov 7, 2023 Issued
Array ( [id] => 19971167 [patent_doc_number] => 12339778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Tokens to indicate completion of data storage [patent_app_type] => utility [patent_app_number] => 18/387320 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18387320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/387320
Tokens to indicate completion of data storage Nov 5, 2023 Issued
Array ( [id] => 20188701 [patent_doc_number] => 12399815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Method and memory controller for optimizing an access scheme for memory access of a host to a data memory [patent_app_type] => utility [patent_app_number] => 18/499525 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4777 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499525 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499525
Method and memory controller for optimizing an access scheme for memory access of a host to a data memory Oct 31, 2023 Issued
Array ( [id] => 19144584 [patent_doc_number] => 20240143501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => DUAL DATA CHANNEL PEAK POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/494841 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494841 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494841
Dual data channel peak power management Oct 25, 2023 Issued
Array ( [id] => 20388206 [patent_doc_number] => 12487932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Controller of storage device [patent_app_type] => utility [patent_app_number] => 18/486165 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/486165
Controller of storage device Oct 12, 2023 Issued
Array ( [id] => 19107303 [patent_doc_number] => 11960407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-16 [patent_title] => Cache purging in a distributed networked system [patent_app_type] => utility [patent_app_number] => 18/482707 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11890 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482707
Cache purging in a distributed networked system Oct 5, 2023 Issued
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