Search

Pierre Miche Bataille

Examiner (ID: 4053, Phone: (571)272-4178 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2136, 2138, 2186, 2752
Total Applications
1979
Issued Applications
1761
Pending Applications
108
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18638164 [patent_doc_number] => 11762766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => Storage device with erase unit level address mapping [patent_app_type] => utility [patent_app_number] => 17/952230 [patent_app_country] => US [patent_app_date] => 2022-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 37309 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/952230
Storage device with erase unit level address mapping Sep 23, 2022 Issued
Array ( [id] => 19609970 [patent_doc_number] => 12158844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Maintaining transactional consistency in columnar engine [patent_app_type] => utility [patent_app_number] => 17/951193 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17951193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/951193
Maintaining transactional consistency in columnar engine Sep 22, 2022 Issued
Array ( [id] => 18342876 [patent_doc_number] => 11640355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-02 [patent_title] => Storage device with multiplane segments, cooperative erasure, metadata and flash management [patent_app_type] => utility [patent_app_number] => 17/951964 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 37306 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17951964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/951964
Storage device with multiplane segments, cooperative erasure, metadata and flash management Sep 22, 2022 Issued
Array ( [id] => 19053204 [patent_doc_number] => 20240095173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => PROVIDING FAIRNESS-BASED ALLOCATION OF CACHES IN PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 17/933232 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933232 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933232
PROVIDING FAIRNESS-BASED ALLOCATION OF CACHES IN PROCESSOR-BASED DEVICES Sep 18, 2022 Abandoned
Array ( [id] => 19052982 [patent_doc_number] => 20240094951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => DYNAMIC ORDERING OF MEMORY DIE PROGRAMMING IN A METABLOCK [patent_app_type] => utility [patent_app_number] => 17/946565 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946565
Dynamic ordering of memory die programming in a metablock Sep 15, 2022 Issued
Array ( [id] => 19053230 [patent_doc_number] => 20240095199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MULTI-INTERFACE MEMORY [patent_app_type] => utility [patent_app_number] => 17/945827 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945827
Multi-interface memory Sep 14, 2022 Issued
Array ( [id] => 18446043 [patent_doc_number] => 11681614 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-20 [patent_title] => Storage device with subdivisions, subdivision query, and write operations [patent_app_type] => utility [patent_app_number] => 17/931506 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 37324 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17931506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/931506
Storage device with subdivisions, subdivision query, and write operations Sep 11, 2022 Issued
Array ( [id] => 18606791 [patent_doc_number] => 11748257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-05 [patent_title] => Host, storage system, and methods with subdivisions and query based write operations [patent_app_type] => utility [patent_app_number] => 17/931516 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 37326 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17931516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/931516
Host, storage system, and methods with subdivisions and query based write operations Sep 11, 2022 Issued
Array ( [id] => 19036532 [patent_doc_number] => 20240086347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => ZQ CALIBRATION CIRCUIT AND METHOD FOR MEMORY INTERFACES [patent_app_type] => utility [patent_app_number] => 17/941790 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941790
ZQ calibration circuit and method for memory interfaces Sep 8, 2022 Issued
Array ( [id] => 18422284 [patent_doc_number] => 20230176748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAM OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/942108 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/942108
Memory device, memory system, and program operation method thereof Sep 8, 2022 Issued
Array ( [id] => 19036518 [patent_doc_number] => 20240086333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => RUNTIME PROTECTION OF SENSITIVE DATA [patent_app_type] => utility [patent_app_number] => 17/930439 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17930439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/930439
Runtime protection of sensitive data Sep 7, 2022 Issued
Array ( [id] => 19022865 [patent_doc_number] => 20240079036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => Standalone Mode [patent_app_type] => utility [patent_app_number] => 17/930034 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17930034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/930034
Standalone mode Sep 5, 2022 Issued
Array ( [id] => 19152576 [patent_doc_number] => 11977487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Data control device, storage system, and data control method [patent_app_type] => utility [patent_app_number] => 17/902078 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 12308 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902078
Data control device, storage system, and data control method Sep 1, 2022 Issued
Array ( [id] => 19182837 [patent_doc_number] => 11989427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Transistor configurations for vertical memory arrays [patent_app_type] => utility [patent_app_number] => 17/823371 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 16424 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823371
Transistor configurations for vertical memory arrays Aug 29, 2022 Issued
Array ( [id] => 18060236 [patent_doc_number] => 20220391322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SERVER RECOVERY FROM A CHANGE IN STORAGE CONTROL CHIP [patent_app_type] => utility [patent_app_number] => 17/820092 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820092 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/820092
Server recovery from a change in storage control chip Aug 15, 2022 Issued
Array ( [id] => 18519881 [patent_doc_number] => 11709772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-25 [patent_title] => Storage system with multiplane segments and cooperative flash management [patent_app_type] => utility [patent_app_number] => 17/877881 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 37309 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877881
Storage system with multiplane segments and cooperative flash management Jul 28, 2022 Issued
Array ( [id] => 19107613 [patent_doc_number] => 11960722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Memory device programming technique for increased bits per cell [patent_app_type] => utility [patent_app_number] => 17/872217 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 17560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872217
Memory device programming technique for increased bits per cell Jul 24, 2022 Issued
Array ( [id] => 19872616 [patent_doc_number] => 12265476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => System, method, apparatus, and computer program product for providing a cache mechanism [patent_app_type] => utility [patent_app_number] => 17/813723 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813723
System, method, apparatus, and computer program product for providing a cache mechanism Jul 19, 2022 Issued
Array ( [id] => 19277065 [patent_doc_number] => 12027196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Memory system, control method, and power control circuit [patent_app_type] => utility [patent_app_number] => 17/856909 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856909 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856909
Memory system, control method, and power control circuit Jun 30, 2022 Issued
Array ( [id] => 19259485 [patent_doc_number] => 12019539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Adaptive configuration of memory devices using host profiling [patent_app_type] => utility [patent_app_number] => 17/856433 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856433
Adaptive configuration of memory devices using host profiling Jun 30, 2022 Issued
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