
Pierre Miche Bataille
Examiner (ID: 12446, Phone: (571)272-4178 , Office: P/2136 )
| Most Active Art Unit | 2136 |
| Art Unit(s) | 2752, 2138, 2186, 2136 |
| Total Applications | 2005 |
| Issued Applications | 1776 |
| Pending Applications | 116 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20820085
[patent_doc_number] => 12675554
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-07-07
[patent_title] => Information processing method, information processing apparatus, and non-transitory computer-readable storage medium
[patent_app_type] => utility
[patent_app_number] => 18/078487
[patent_app_country] => US
[patent_app_date] => 2022-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 18711
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078487
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/078487 | Information processing method, information processing apparatus, and non-transitory computer-readable storage medium | Dec 8, 2022 | Issued |
Array
(
[id] => 19205150
[patent_doc_number] => 20240177049
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => CONFIDENTIAL TUNING OF PRE-TRAINED MACHINE LEARNING MODELS
[patent_app_type] => utility
[patent_app_number] => 18/058840
[patent_app_country] => US
[patent_app_date] => 2022-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9180
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058840
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/058840 | Confidential tuning of pre-trained machine learning models | Nov 24, 2022 | Issued |
Array
(
[id] => 18306476
[patent_doc_number] => 20230110376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-13
[patent_title] => RESOURCE-AWARE COMPRESSION
[patent_app_type] => utility
[patent_app_number] => 18/058534
[patent_app_country] => US
[patent_app_date] => 2022-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4981
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058534
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/058534 | Resource-aware compression | Nov 22, 2022 | Issued |
Array
(
[id] => 18242361
[patent_doc_number] => 20230074672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => HIGH-SPEED DATA TRANSFERS THROUGH STORAGE DEVICE CONNECTORS
[patent_app_type] => utility
[patent_app_number] => 17/986883
[patent_app_country] => US
[patent_app_date] => 2022-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17986883
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/986883 | High-speed data transfers through storage device connectors | Nov 13, 2022 | Issued |
Array
(
[id] => 20145693
[patent_doc_number] => 12380036
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-05
[patent_title] => Cache optimization mechanism
[patent_app_type] => utility
[patent_app_number] => 17/986528
[patent_app_country] => US
[patent_app_date] => 2022-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 1104
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17986528
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/986528 | Cache optimization mechanism | Nov 13, 2022 | Issued |
Array
(
[id] => 18614758
[patent_doc_number] => 20230281495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => EQUILIBRIUM SOLUTION SEARCH METHOD AND INFORMATION PROCESSING APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/983855
[patent_app_country] => US
[patent_app_date] => 2022-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7233
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983855
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/983855 | EQUILIBRIUM SOLUTION SEARCH METHOD AND INFORMATION PROCESSING APPARATUS | Nov 8, 2022 | Pending |
Array
(
[id] => 19159758
[patent_doc_number] => 20240152465
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => HYBRID SCHEME FOR PERFORMING TRANSLATION LOOKASIDE BUFFER (TLB) SHOOTDOWNS
[patent_app_type] => utility
[patent_app_number] => 18/053103
[patent_app_country] => US
[patent_app_date] => 2022-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4597
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053103
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/053103 | Hybrid scheme for performing translation lookaside buffer (TLB) shootdowns | Nov 6, 2022 | Issued |
Array
(
[id] => 18364450
[patent_doc_number] => 20230146041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => NON-VOLATILE MEMORY DEVICE INCLUDING MULTI-STACK MEMORY BLOCK AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/052428
[patent_app_country] => US
[patent_app_date] => 2022-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14003
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052428
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/052428 | Non-volatile memory device including multi-stack memory block and operating method thereof | Nov 2, 2022 | Issued |
Array
(
[id] => 20550607
[patent_doc_number] => 12561401
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-24
[patent_title] => Information processing device, input control method and program
[patent_app_type] => utility
[patent_app_number] => 17/974857
[patent_app_country] => US
[patent_app_date] => 2022-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 26
[patent_no_of_words] => 6295
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974857
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/974857 | Information processing device, input control method and program | Oct 26, 2022 | Issued |
Array
(
[id] => 19340586
[patent_doc_number] => 12050776
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Apparatus with response completion pacing
[patent_app_type] => utility
[patent_app_number] => 18/049973
[patent_app_country] => US
[patent_app_date] => 2022-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6159
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049973
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/049973 | Apparatus with response completion pacing | Oct 25, 2022 | Issued |
Array
(
[id] => 18531892
[patent_doc_number] => 20230236964
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-27
[patent_title] => STORAGE CONTROLLER DEALLOCATING MEMORY BLOCK, METHOD OF OPERATING THE SAME, AND METHOD OF OPERATING STORAGE DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/049380
[patent_app_country] => US
[patent_app_date] => 2022-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11980
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049380
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/049380 | Storage controller deallocating memory block, method of operating the same, and method of operating storage device including the same | Oct 24, 2022 | Issued |
Array
(
[id] => 19678088
[patent_doc_number] => 12189949
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Bit error management in memory devices
[patent_app_type] => utility
[patent_app_number] => 18/049121
[patent_app_country] => US
[patent_app_date] => 2022-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 12517
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049121
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/049121 | Bit error management in memory devices | Oct 23, 2022 | Issued |
Array
(
[id] => 19293138
[patent_doc_number] => 12032491
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Method for remapping virtual address to physical address and address remapping unit
[patent_app_type] => utility
[patent_app_number] => 18/047784
[patent_app_country] => US
[patent_app_date] => 2022-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7112
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047784
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/047784 | Method for remapping virtual address to physical address and address remapping unit | Oct 18, 2022 | Issued |
Array
(
[id] => 19293138
[patent_doc_number] => 12032491
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Method for remapping virtual address to physical address and address remapping unit
[patent_app_type] => utility
[patent_app_number] => 18/047784
[patent_app_country] => US
[patent_app_date] => 2022-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7112
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047784
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/047784 | Method for remapping virtual address to physical address and address remapping unit | Oct 18, 2022 | Issued |
Array
(
[id] => 19293138
[patent_doc_number] => 12032491
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Method for remapping virtual address to physical address and address remapping unit
[patent_app_type] => utility
[patent_app_number] => 18/047784
[patent_app_country] => US
[patent_app_date] => 2022-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7112
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047784
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/047784 | Method for remapping virtual address to physical address and address remapping unit | Oct 18, 2022 | Issued |
Array
(
[id] => 19293138
[patent_doc_number] => 12032491
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Method for remapping virtual address to physical address and address remapping unit
[patent_app_type] => utility
[patent_app_number] => 18/047784
[patent_app_country] => US
[patent_app_date] => 2022-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7112
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047784
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/047784 | Method for remapping virtual address to physical address and address remapping unit | Oct 18, 2022 | Issued |
Array
(
[id] => 19313354
[patent_doc_number] => 12039168
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-16
[patent_title] => Multiple version write pending support in shared global memory
[patent_app_type] => utility
[patent_app_number] => 17/965841
[patent_app_country] => US
[patent_app_date] => 2022-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6354
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 400
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17965841
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/965841 | Multiple version write pending support in shared global memory | Oct 13, 2022 | Issued |
Array
(
[id] => 19764577
[patent_doc_number] => 12222867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => Processor, computer system, and method for flushing hierarchical cache structure based on a designated key identification code and a designated address
[patent_app_type] => utility
[patent_app_number] => 18/046642
[patent_app_country] => US
[patent_app_date] => 2022-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4658
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046642
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/046642 | Processor, computer system, and method for flushing hierarchical cache structure based on a designated key identification code and a designated address | Oct 13, 2022 | Issued |
Array
(
[id] => 18407660
[patent_doc_number] => 20230169013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-01
[patent_title] => ADDRESS TRANSLATION CACHE AND SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/965700
[patent_app_country] => US
[patent_app_date] => 2022-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12487
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17965700
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/965700 | Address translation cache and system including the same | Oct 12, 2022 | Issued |
Array
(
[id] => 19398754
[patent_doc_number] => 12073120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-27
[patent_title] => Activate information on preceding command
[patent_app_type] => utility
[patent_app_number] => 17/965584
[patent_app_country] => US
[patent_app_date] => 2022-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 10783
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17965584
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/965584 | Activate information on preceding command | Oct 12, 2022 | Issued |