
Prashant J. Khatri
Examiner (ID: 7506)
| Most Active Art Unit | 1783 |
| Art Unit(s) | 1783, 1794 |
| Total Applications | 978 |
| Issued Applications | 550 |
| Pending Applications | 82 |
| Abandoned Applications | 370 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11758571
[patent_doc_number] => 20170205439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-20
[patent_title] => 'SPEED ESTIMATION SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 15/002364
[patent_app_country] => US
[patent_app_date] => 2016-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2663
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002364
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/002364 | Speed estimation systems | Jan 19, 2016 | Issued |
Array
(
[id] => 11246506
[patent_doc_number] => 09472556
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-10-18
[patent_title] => 'SOI lateral bipolar for integrated-injection logic SRAM'
[patent_app_type] => utility
[patent_app_number] => 14/997176
[patent_app_country] => US
[patent_app_date] => 2016-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7087
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997176
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/997176 | SOI lateral bipolar for integrated-injection logic SRAM | Jan 14, 2016 | Issued |
Array
(
[id] => 11000088
[patent_doc_number] => 20160197035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-07
[patent_title] => 'STACKED MULTILAYER STRUCTURE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/996071
[patent_app_country] => US
[patent_app_date] => 2016-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 11611
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14996071
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/996071 | Stacked multilayer structure and manufacturing method thereof | Jan 13, 2016 | Issued |
Array
(
[id] => 10787461
[patent_doc_number] => 20160133617
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-12
[patent_title] => 'FORMING A PANEL OF TRIPLE STACK SEMICONDUCTOR PACKAGES'
[patent_app_type] => utility
[patent_app_number] => 14/988192
[patent_app_country] => US
[patent_app_date] => 2016-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 3112
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14988192
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/988192 | Forming a panel of triple stack semiconductor packages | Jan 4, 2016 | Issued |
Array
(
[id] => 11818241
[patent_doc_number] => 09722208
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-01
[patent_title] => 'Light-emitting devices using thin film electrode with refractive index optimized capping layer for reduction of plasmonic energy loss'
[patent_app_type] => utility
[patent_app_number] => 14/984857
[patent_app_country] => US
[patent_app_date] => 2015-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 5803
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984857
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/984857 | Light-emitting devices using thin film electrode with refractive index optimized capping layer for reduction of plasmonic energy loss | Dec 29, 2015 | Issued |
Array
(
[id] => 11687577
[patent_doc_number] => 09685627
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-20
[patent_title] => 'Function panel and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/980266
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 50
[patent_no_of_words] => 17087
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980266
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980266 | Function panel and manufacturing method thereof | Dec 27, 2015 | Issued |
Array
(
[id] => 10984036
[patent_doc_number] => 20160180980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'BETA VOLTAIC BATTERY AND METHOD OF PREPARING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/976477
[patent_app_country] => US
[patent_app_date] => 2015-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4909
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976477
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/976477 | Beta voltaic battery and method of preparing the same | Dec 20, 2015 | Issued |
Array
(
[id] => 11708456
[patent_doc_number] => 20170176956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'CONTROL SYSTEM USING INPUT-AWARE STACKER'
[patent_app_type] => utility
[patent_app_number] => 14/972729
[patent_app_country] => US
[patent_app_date] => 2015-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6526
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972729
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/972729 | CONTROL SYSTEM USING INPUT-AWARE STACKER | Dec 16, 2015 | Abandoned |
Array
(
[id] => 11333811
[patent_doc_number] => 09525064
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-12-20
[patent_title] => 'Channel-last replacement metal-gate vertical field effect transistor'
[patent_app_type] => utility
[patent_app_number] => 14/970977
[patent_app_country] => US
[patent_app_date] => 2015-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 40
[patent_no_of_words] => 5240
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970977
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/970977 | Channel-last replacement metal-gate vertical field effect transistor | Dec 15, 2015 | Issued |
Array
(
[id] => 10758537
[patent_doc_number] => 20160104689
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-14
[patent_title] => 'SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING'
[patent_app_type] => utility
[patent_app_number] => 14/969779
[patent_app_country] => US
[patent_app_date] => 2015-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6872
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969779
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/969779 | Semiconductor die mount by conformal die coating | Dec 14, 2015 | Issued |
Array
(
[id] => 11701860
[patent_doc_number] => 09691785
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-27
[patent_title] => 'Three-dimensional structured memory devices'
[patent_app_type] => utility
[patent_app_number] => 14/942533
[patent_app_country] => US
[patent_app_date] => 2015-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 28
[patent_no_of_words] => 7467
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942533
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/942533 | Three-dimensional structured memory devices | Nov 15, 2015 | Issued |
Array
(
[id] => 10693521
[patent_doc_number] => 20160039667
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-11
[patent_title] => 'METHOD TO PACKAGE MULTIPLE MEMS SENSORS AND ACTUATORS AT DIFFERENT GASES AND CAVITY PRESSURES'
[patent_app_type] => utility
[patent_app_number] => 14/887622
[patent_app_country] => US
[patent_app_date] => 2015-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5190
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14887622
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/887622 | Method to package multiple mems sensors and actuators at different gases and cavity pressures | Oct 19, 2015 | Issued |
Array
(
[id] => 11753359
[patent_doc_number] => 09711377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-18
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/886088
[patent_app_country] => US
[patent_app_date] => 2015-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 50
[patent_no_of_words] => 15126
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 491
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14886088
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/886088 | Method of manufacturing semiconductor device | Oct 17, 2015 | Issued |
Array
(
[id] => 11660262
[patent_doc_number] => 09673277
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-06
[patent_title] => 'Methods and apparatus for forming horizontal gate all around device structures'
[patent_app_type] => utility
[patent_app_number] => 14/885521
[patent_app_country] => US
[patent_app_date] => 2015-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4855
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14885521
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/885521 | Methods and apparatus for forming horizontal gate all around device structures | Oct 15, 2015 | Issued |
Array
(
[id] => 10779955
[patent_doc_number] => 20160126111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-05
[patent_title] => 'METHODS OF MANUFACTURING A PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN PLACE OF A LOW-RESISTIVITY HANDLE LAYER'
[patent_app_type] => utility
[patent_app_number] => 14/885243
[patent_app_country] => US
[patent_app_date] => 2015-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6768
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14885243
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/885243 | Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer | Oct 15, 2015 | Issued |
Array
(
[id] => 11328320
[patent_doc_number] => 20160358931
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-08
[patent_title] => 'METHODS OF FABRICATING EMBEDDED ELECTRONIC DEVICES INCLUDING CHARGE TRAP MEMORY CELLS'
[patent_app_type] => utility
[patent_app_number] => 14/885371
[patent_app_country] => US
[patent_app_date] => 2015-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 8001
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14885371
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/885371 | Methods of fabricating embedded electronic devices including charge trap memory cells | Oct 15, 2015 | Issued |
Array
(
[id] => 11495358
[patent_doc_number] => 20170069543
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/884746
[patent_app_country] => US
[patent_app_date] => 2015-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4800
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14884746
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/884746 | Method for fabricating semiconductor device | Oct 14, 2015 | Issued |
Array
(
[id] => 10689536
[patent_doc_number] => 20160035682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-04
[patent_title] => 'INTEGRATED CIRCUIT WITH BACKSIDE STRUCTURES TO REDUCE SUBSTRATE WARP'
[patent_app_type] => utility
[patent_app_number] => 14/881365
[patent_app_country] => US
[patent_app_date] => 2015-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 4740
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14881365
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/881365 | Integrated circuit with backside structures to reduce substrate warp | Oct 12, 2015 | Issued |
Array
(
[id] => 11300679
[patent_doc_number] => 09508689
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-29
[patent_title] => 'Electrical connector between die pad and z-interconnect for stacked die assemblies'
[patent_app_type] => utility
[patent_app_number] => 14/871185
[patent_app_country] => US
[patent_app_date] => 2015-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 28
[patent_no_of_words] => 9299
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871185
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/871185 | Electrical connector between die pad and z-interconnect for stacked die assemblies | Sep 29, 2015 | Issued |
Array
(
[id] => 14064199
[patent_doc_number] => 10236406
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-19
[patent_title] => Systems and methods for targeted annealing of photovoltaic structures
[patent_app_type] => utility
[patent_app_number] => 14/866817
[patent_app_country] => US
[patent_app_date] => 2015-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 8340
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866817
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/866817 | Systems and methods for targeted annealing of photovoltaic structures | Sep 24, 2015 | Issued |