Search

Prasith Thammavong

Examiner (ID: 9450, Phone: (571)270-1040 , Office: P/2137 )

Most Active Art Unit
2137
Art Unit(s)
2187, 2137
Total Applications
681
Issued Applications
541
Pending Applications
67
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11621893 [patent_doc_number] => 20170132080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'REBUILD PRIORITIZATION DURING A PLURALITY OF CONCURRENT DATA OBJECT WRITE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 15/414338 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9014 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414338 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414338
Rebuild prioritization during a plurality of concurrent data object write operations Jan 23, 2017 Issued
Array ( [id] => 11621894 [patent_doc_number] => 20170132081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'PRIORITY BASED REBUILDING' [patent_app_type] => utility [patent_app_number] => 15/414452 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9025 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414452
Priority based rebuilding Jan 23, 2017 Issued
Array ( [id] => 14918229 [patent_doc_number] => 10430434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Managing transformed snapshots in a storage system [patent_app_type] => utility [patent_app_number] => 15/411471 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9819 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411471
Managing transformed snapshots in a storage system Jan 19, 2017 Issued
Array ( [id] => 15670719 [patent_doc_number] => 10599590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Uniform memory access architecture [patent_app_type] => utility [patent_app_number] => 15/365005 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365005 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365005
Uniform memory access architecture Nov 29, 2016 Issued
Array ( [id] => 14204605 [patent_doc_number] => 10269421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Latch caching of sequential data [patent_app_type] => utility [patent_app_number] => 15/364831 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 14973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364831 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364831
Latch caching of sequential data Nov 29, 2016 Issued
Array ( [id] => 12775684 [patent_doc_number] => 20180150396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => MANAGING LOWEST POINT OF COHERENCY (LPC) MEMORY USING A SERVICE LAYER ADAPTER [patent_app_type] => utility [patent_app_number] => 15/364458 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364458 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364458
Managing lowest point of coherency (LPC) memory using a service layer adapter Nov 29, 2016 Issued
Array ( [id] => 16185931 [patent_doc_number] => 10719263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Method of handling page fault in nonvolatile main memory system [patent_app_type] => utility [patent_app_number] => 15/364628 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364628
Method of handling page fault in nonvolatile main memory system Nov 29, 2016 Issued
Array ( [id] => 14009615 [patent_doc_number] => 10223266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Extended store forwarding for store misses without cache allocate [patent_app_type] => utility [patent_app_number] => 15/364411 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364411 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364411
Extended store forwarding for store misses without cache allocate Nov 29, 2016 Issued
Array ( [id] => 11501576 [patent_doc_number] => 20170075762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'ONLINE DISK REPLACEMENT/REMOVAL' [patent_app_type] => utility [patent_app_number] => 15/362180 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/362180
Online disk replacement/removal Nov 27, 2016 Issued
Array ( [id] => 14149607 [patent_doc_number] => 10255184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Memory access architecture with coherence [patent_app_type] => utility [patent_app_number] => 15/345226 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345226
Memory access architecture with coherence Nov 6, 2016 Issued
Array ( [id] => 15013421 [patent_doc_number] => 10452860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => System, electronic apparatus and method [patent_app_type] => utility [patent_app_number] => 15/345364 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345364 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345364
System, electronic apparatus and method Nov 6, 2016 Issued
Array ( [id] => 13361533 [patent_doc_number] => 20180232306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => DATA PROCESSING APPARATUS, AND DATA PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 15/754331 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15754331 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/754331
Data processing apparatus, and data processing method Oct 26, 2016 Issued
Array ( [id] => 11326947 [patent_doc_number] => 20160357559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'SYSTEMS AND METHODS FOR LOAD CANCELING IN A PROCESSOR THAT IS CONNECTED TO AN EXTERNAL INTERCONNECT FABRIC' [patent_app_type] => utility [patent_app_number] => 15/244873 [patent_app_country] => US [patent_app_date] => 2016-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15244873 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/244873
Systems and methods for load cancelling in a processor that is connected to an external interconnect fabric Aug 22, 2016 Issued
Array ( [id] => 16535065 [patent_doc_number] => 10877665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Apparatus and method to provide cache move with non-volatile mass memory system [patent_app_type] => utility [patent_app_number] => 15/235425 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9599 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235425 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235425
Apparatus and method to provide cache move with non-volatile mass memory system Aug 11, 2016 Issued
Array ( [id] => 13214333 [patent_doc_number] => 10121541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Semiconductor device and information processing system [patent_app_type] => utility [patent_app_number] => 15/228631 [patent_app_country] => US [patent_app_date] => 2016-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 17791 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228631 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/228631
Semiconductor device and information processing system Aug 3, 2016 Issued
Array ( [id] => 11938643 [patent_doc_number] => 20170242793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'PROVIDING SCALABLE DYNAMIC RANDOM ACCESS MEMORY (DRAM) CACHE MANAGEMENT USING DRAM CACHE INDICATOR CACHES' [patent_app_type] => utility [patent_app_number] => 15/228320 [patent_app_country] => US [patent_app_date] => 2016-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10909 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/228320
Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches Aug 3, 2016 Issued
Array ( [id] => 11494298 [patent_doc_number] => 20170068483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'STORAGE DEVICE, COMPUTER READABLE RECORDING MEDIUM, AND STORAGE DEVICE CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 15/228478 [patent_app_country] => US [patent_app_date] => 2016-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11837 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228478 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/228478
Storage device, computer readable recording medium, and storage device control method Aug 3, 2016 Issued
Array ( [id] => 13721681 [patent_doc_number] => 20170371795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => Multi-Level System Memory With Near Memory Scrubbing Based On Predicted Far Memory Idle Time [patent_app_type] => utility [patent_app_number] => 15/193952 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193952 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/193952
Multi-level system memory with near memory scrubbing based on predicted far memory idle time Jun 26, 2016 Issued
Array ( [id] => 12351858 [patent_doc_number] => 09952794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Transient compression layer [patent_app_type] => utility [patent_app_number] => 15/194179 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/194179
Transient compression layer Jun 26, 2016 Issued
Array ( [id] => 13859899 [patent_doc_number] => 10191668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Method for dynamically modeling medium error evolution to predict disk failure [patent_app_type] => utility [patent_app_number] => 15/194189 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194189 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/194189
Method for dynamically modeling medium error evolution to predict disk failure Jun 26, 2016 Issued
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