Search

Preeti Kumar

Examiner (ID: 5654, Phone: (571)272-1320 , Office: P/1764 )

Most Active Art Unit
1764
Art Unit(s)
1751, 1796, 1764, 1761
Total Applications
720
Issued Applications
185
Pending Applications
132
Abandoned Applications
418

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19484309 [patent_doc_number] => 20240332351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/743906 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743906
Capacitor structure and method for manufacturing the same Jun 13, 2024 Issued
Array ( [id] => 19452854 [patent_doc_number] => 20240312984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => Carbon and/or Oxygen Doped Polysilicon Resistor [patent_app_type] => utility [patent_app_number] => 18/677190 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677190 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677190
Carbon and/or Oxygen Doped Polysilicon Resistor May 28, 2024 Pending
Array ( [id] => 20470968 [patent_doc_number] => 12527014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Amorphous bottom electrode structure for MIM capacitors [patent_app_type] => utility [patent_app_number] => 18/664389 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 9306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664389 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664389
Amorphous bottom electrode structure for MIM capacitors May 14, 2024 Issued
Array ( [id] => 19407030 [patent_doc_number] => 20240290541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => INTEGRATION SCHEME FOR BREAKDOWN VOLTAGE ENHANCEMENT OF A PIEZOELECTRIC METAL-INSULATOR-METAL DEVICE [patent_app_type] => utility [patent_app_number] => 18/659337 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659337 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659337
INTEGRATION SCHEME FOR BREAKDOWN VOLTAGE ENHANCEMENT OF A PIEZOELECTRIC METAL-INSULATOR-METAL DEVICE May 8, 2024 Pending
Array ( [id] => 19407140 [patent_doc_number] => 20240290651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SELF-ASSEMBLED GUIDED HOLE AND VIA PATTERNING OVER GRATING [patent_app_type] => utility [patent_app_number] => 18/655567 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655567
SELF-ASSEMBLED GUIDED HOLE AND VIA PATTERNING OVER GRATING May 5, 2024 Issued
Array ( [id] => 20134039 [patent_doc_number] => 12376370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Control of locos structure thickness without a mask [patent_app_type] => utility [patent_app_number] => 18/632439 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 1165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632439 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632439
Control of locos structure thickness without a mask Apr 10, 2024 Issued
Array ( [id] => 20113170 [patent_doc_number] => 12363925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Schottky barrier diode with reduced leakage current and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/629967 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629967
Schottky barrier diode with reduced leakage current and method of forming the same Apr 8, 2024 Issued
Array ( [id] => 20268668 [patent_doc_number] => 12439681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/613151 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613151
Semiconductor device and method for fabricating the same Mar 21, 2024 Issued
Array ( [id] => 19252869 [patent_doc_number] => 20240203866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => INTEGRATED CIRCUITS (ICs) EMPLOYING DIRECTLY COUPLED METAL LINES BETWEEN VERTICALLY-ADJACENT INTERCONNECT LAYERS FOR REDUCED COUPLING RESISTANCE, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/590242 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590242
INTEGRATED CIRCUITS (ICs) EMPLOYING DIRECTLY COUPLED METAL LINES BETWEEN VERTICALLY-ADJACENT INTERCONNECT LAYERS FOR REDUCED COUPLING RESISTANCE, AND RELATED METHODS Feb 27, 2024 Pending
Array ( [id] => 20198444 [patent_doc_number] => 20250275154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => VERTICAL RESISTIVE MEMORY DEVICE AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 18/584165 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584165
VERTICAL RESISTIVE MEMORY DEVICE AND RELATED METHOD Feb 21, 2024 Pending
Array ( [id] => 19988640 [patent_doc_number] => 20250126862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/582951 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582951
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Feb 20, 2024 Pending
Array ( [id] => 19966698 [patent_doc_number] => 12336236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Semiconductor device isolation features [patent_app_type] => utility [patent_app_number] => 18/442794 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 47 [patent_no_of_words] => 12265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442794
Semiconductor device isolation features Feb 14, 2024 Issued
Array ( [id] => 19407415 [patent_doc_number] => 20240290926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => Display Device [patent_app_type] => utility [patent_app_number] => 18/443202 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443202
Display Device Feb 14, 2024 Pending
Array ( [id] => 20469409 [patent_doc_number] => 12525451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures [patent_app_type] => utility [patent_app_number] => 18/440452 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440452 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440452
Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures Feb 12, 2024 Issued
Array ( [id] => 19221664 [patent_doc_number] => 20240186368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING CAPACITOR AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/434954 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434954 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434954
Semiconductor devices including capacitor and methods of manufacturing the semiconductor devices Feb 6, 2024 Issued
Array ( [id] => 19269464 [patent_doc_number] => 20240213168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/434711 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434711
Semiconductor package and method of manufacturing the same Feb 5, 2024 Issued
Array ( [id] => 20155061 [patent_doc_number] => 20250254899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SCHOTTKY BARRIER DIODE [patent_app_type] => utility [patent_app_number] => 18/430955 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430955
SCHOTTKY BARRIER DIODE Feb 1, 2024 Pending
Array ( [id] => 20141009 [patent_doc_number] => 20250248053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => CHOKE FILTERS IMPLEMENTED USING SUBSTRATE MATERIALS [patent_app_type] => utility [patent_app_number] => 18/424150 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424150
CHOKE FILTERS IMPLEMENTED USING SUBSTRATE MATERIALS Jan 25, 2024 Pending
Array ( [id] => 19727134 [patent_doc_number] => 20250029885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SEMICONDUCTOR PACKAGE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/416151 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416151
SEMICONDUCTOR PACKAGE AND METHODS OF FORMING THE SAME Jan 17, 2024 Pending
Array ( [id] => 19161248 [patent_doc_number] => 20240153955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/414540 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414540
SEMICONDUCTOR DEVICE Jan 16, 2024 Pending
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