Search

Preeti Kumar

Examiner (ID: 5654, Phone: (571)272-1320 , Office: P/1764 )

Most Active Art Unit
1764
Art Unit(s)
1751, 1796, 1764, 1761
Total Applications
720
Issued Applications
185
Pending Applications
132
Abandoned Applications
418

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18415957 [patent_doc_number] => 11670502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => SiC MOSFET and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/235103 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/235103
SiC MOSFET and method for manufacturing the same Apr 19, 2021 Issued
Array ( [id] => 17752719 [patent_doc_number] => 20220230924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => MULTI-FIN VERTICAL FIELD EFFECT TRANSISTOR AND SINGLE-FIN VERTICAL FIELD EFFECT TRANSISTOR ON A SINGLE INTEGRATED CIRCUIT CHIP [patent_app_type] => utility [patent_app_number] => 17/223803 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223803
Multi-fin vertical field effect transistor and single-fin vertical field effect transistor on a single integrated circuit chip Apr 5, 2021 Issued
Array ( [id] => 18669984 [patent_doc_number] => 11776896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Capacitor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/219282 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219282
Capacitor device and manufacturing method thereof Mar 30, 2021 Issued
Array ( [id] => 20484060 [patent_doc_number] => 12532539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Method for manufacturing a SeOI integrated circuit chip [patent_app_type] => utility [patent_app_number] => 17/995791 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17995791 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/995791
Method for manufacturing a SeOI integrated circuit chip Mar 28, 2021 Issued
Array ( [id] => 16981603 [patent_doc_number] => 20210225840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => POLYSILICON STRUCTURE INCLUDING PROTECTIVE LAYER [patent_app_type] => utility [patent_app_number] => 17/205579 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/205579
Polysilicon structure including protective layer Mar 17, 2021 Issued
Array ( [id] => 18670134 [patent_doc_number] => 11777046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Energy storage [patent_app_type] => utility [patent_app_number] => 17/201719 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11534 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201719
Energy storage Mar 14, 2021 Issued
Array ( [id] => 18804479 [patent_doc_number] => 11837643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Method for manufacturing memory device [patent_app_type] => utility [patent_app_number] => 17/200865 [patent_app_country] => US [patent_app_date] => 2021-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200865
Method for manufacturing memory device Mar 13, 2021 Issued
Array ( [id] => 16966113 [patent_doc_number] => 20210217612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => FORMING A PLANAR SURFACE OF A III-NITRIDE MATERIAL [patent_app_type] => utility [patent_app_number] => 17/197540 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197540
Forming a planar surface of a III-nitride material Mar 9, 2021 Issued
Array ( [id] => 18190582 [patent_doc_number] => 11581183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom [patent_app_type] => utility [patent_app_number] => 17/192882 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7010 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192882
Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom Mar 3, 2021 Issued
Array ( [id] => 17855435 [patent_doc_number] => 20220285478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => COMPENSATION CAPACITORS LAYOUT IN SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/191273 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191273
Compensation capacitors layout in semiconductor device Mar 2, 2021 Issued
Array ( [id] => 16905031 [patent_doc_number] => 20210183947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => THREE DIMENSIONAL MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 17/187213 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187213
Three dimensional memory arrays Feb 25, 2021 Issued
Array ( [id] => 16905145 [patent_doc_number] => 20210184061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => CAPACITORS IN GROOVES [patent_app_type] => utility [patent_app_number] => 17/185395 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185395
Capacitors in grooves Feb 24, 2021 Issued
Array ( [id] => 17347200 [patent_doc_number] => 20220013531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => Method Of Forming Split Gate Memory Cells With Thinner Tunnel Oxide [patent_app_type] => utility [patent_app_number] => 17/179057 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179057
Method of forming split gate memory cells with thinner tunnel oxide Feb 17, 2021 Issued
Array ( [id] => 16873732 [patent_doc_number] => 20210167199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => GROUP III-NITRIDE HIGH-ELECTRON MOBILITY TRANSISTORS WITH GATE CONNECTED BURIED P-TYPE LAYERS AND PROCESS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/172669 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172669 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172669
Group III-nitride high-electron mobility transistors with gate connected buried p-type layers and process for making the same Feb 9, 2021 Issued
Array ( [id] => 17764899 [patent_doc_number] => 20220238512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => DIELECTRIC LATTICE WITH PASSIVE COMPONENT CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/248390 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248390
Dielectric lattice with passive component circuits Jan 21, 2021 Issued
Array ( [id] => 18343501 [patent_doc_number] => 11640985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Trench isolation for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 17/151083 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 225 [patent_no_of_words] => 73477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151083 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151083
Trench isolation for advanced integrated circuit structure fabrication Jan 14, 2021 Issued
Array ( [id] => 17188787 [patent_doc_number] => 20210335672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => Method For Making Semiconductor Device By Adopting Stress Memorization Technique [patent_app_type] => utility [patent_app_number] => 17/147984 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 561 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147984
Method for making semiconductor device by adopting stress memorization technique Jan 12, 2021 Issued
Array ( [id] => 18548332 [patent_doc_number] => 11721693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Semiconductor devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/145830 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145830
Semiconductor devices and methods of manufacturing thereof Jan 10, 2021 Issued
Array ( [id] => 18175276 [patent_doc_number] => 11574995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => High voltage isolated microelectronic device [patent_app_type] => utility [patent_app_number] => 17/138059 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4145 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138059
High voltage isolated microelectronic device Dec 29, 2020 Issued
Array ( [id] => 17708950 [patent_doc_number] => 20220208958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/136075 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136075
Capacitor structure and method for manufacturing the same Dec 28, 2020 Issued
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