Search

Preeti Kumar

Examiner (ID: 5654, Phone: (571)272-1320 , Office: P/1764 )

Most Active Art Unit
1764
Art Unit(s)
1751, 1796, 1764, 1761
Total Applications
720
Issued Applications
185
Pending Applications
132
Abandoned Applications
418

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19532020 [patent_doc_number] => 20240355922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR DEVICE, POWER CONVERSION APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/413662 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413662
SEMICONDUCTOR DEVICE, POWER CONVERSION APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Jan 15, 2024 Pending
Array ( [id] => 19146284 [patent_doc_number] => 20240145313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MULTI-FIN VERTICAL FIELD EFFECT TRANSISTOR AND SINGLE-FIN VERTICAL FIELD EFFECT TRANSISTOR ON A SINGLE INTEGRATED CIRCUIT CHIP [patent_app_type] => utility [patent_app_number] => 18/407020 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407020 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/407020
Multi-fin vertical field effect transistor and single-fin vertical field effect transistor on a single integrated circuit chip Jan 7, 2024 Issued
Array ( [id] => 19161251 [patent_doc_number] => 20240153958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/406155 [patent_app_country] => US [patent_app_date] => 2024-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406155
Semiconductor device structure and methods of forming the same Jan 6, 2024 Issued
Array ( [id] => 19928270 [patent_doc_number] => 12302581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Semiconductor memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/398378 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 1169 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18398378 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/398378
Semiconductor memory device and method of manufacturing the same Dec 27, 2023 Issued
Array ( [id] => 20072285 [patent_doc_number] => 20250210507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => STACKED TRENCH CAPACITORS AND METHODS OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 18/391742 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391742 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/391742
STACKED TRENCH CAPACITORS AND METHODS OF MAKING THEREOF Dec 20, 2023 Pending
Array ( [id] => 20072093 [patent_doc_number] => 20250210315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => MODULAR PROCESSING CHAMBERS AND RELATED HEATING CONFIGURATIONS, METHODS, APPARATUS, AND MODULES FOR SEMICONDUCTOR MANUFACTURING [patent_app_type] => utility [patent_app_number] => 18/393086 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393086
MODULAR PROCESSING CHAMBERS AND RELATED HEATING CONFIGURATIONS, METHODS, APPARATUS, AND MODULES FOR SEMICONDUCTOR MANUFACTURING Dec 20, 2023 Pending
Array ( [id] => 19071094 [patent_doc_number] => 20240105520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => TRENCH PLUG HARDMASK FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 18/534219 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534219
Trench plug hardmask for advanced integrated circuit structure fabrication Dec 7, 2023 Issued
Array ( [id] => 19741284 [patent_doc_number] => 12218130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Semiconductor structure cutting process and structures formed thereby [patent_app_type] => utility [patent_app_number] => 18/526290 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 69 [patent_no_of_words] => 10675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526290 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526290
Semiconductor structure cutting process and structures formed thereby Nov 30, 2023 Issued
Array ( [id] => 20361752 [patent_doc_number] => 12477770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Group III-nitride high-electron mobility transistors with buried p-type layers and process for making the same [patent_app_type] => utility [patent_app_number] => 18/523174 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 24034 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523174
Group III-nitride high-electron mobility transistors with buried p-type layers and process for making the same Nov 28, 2023 Issued
Array ( [id] => 19054915 [patent_doc_number] => 20240096884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => METHOD OF MAKING POLYSILICON STRUCTURE INCLUDING PROTECTIVE LAYER [patent_app_type] => utility [patent_app_number] => 18/521404 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521404 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521404
Method of making polysilicon structure including protective layer Nov 27, 2023 Issued
Array ( [id] => 19038091 [patent_doc_number] => 20240087906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => ANTI-OXIDATION LAYER TO PREVENT DIELECTRIC LOSS FROM PLANARIZATION PROCESS [patent_app_type] => utility [patent_app_number] => 18/514010 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/514010
Anti-oxidation layer to prevent dielectric loss from planarization process Nov 19, 2023 Issued
Array ( [id] => 19176253 [patent_doc_number] => 20240162227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/513619 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513619
Semiconductor device structure including forksheet transistors and methods of forming the same Nov 18, 2023 Issued
Array ( [id] => 19654423 [patent_doc_number] => 12176223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Integrated circuit package supports [patent_app_type] => utility [patent_app_number] => 18/502244 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 48 [patent_no_of_words] => 17431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502244
Integrated circuit package supports Nov 5, 2023 Issued
Array ( [id] => 19936885 [patent_doc_number] => 12310106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Devices including stacked nanosheet transistors [patent_app_type] => utility [patent_app_number] => 18/499258 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 1011 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499258
Devices including stacked nanosheet transistors Oct 31, 2023 Issued
Array ( [id] => 19671065 [patent_doc_number] => 12183838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-31 [patent_title] => Passivation of infrared detectors using oxide layer [patent_app_type] => utility [patent_app_number] => 18/490456 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2446 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/490456
Passivation of infrared detectors using oxide layer Oct 18, 2023 Issued
Array ( [id] => 19116405 [patent_doc_number] => 20240128155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/379841 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379841 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/379841
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Oct 12, 2023 Pending
Array ( [id] => 20540528 [patent_doc_number] => 12557617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Continuous gate and fin spacer for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 18/376763 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 69185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376763 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376763
Continuous gate and fin spacer for advanced integrated circuit structure fabrication Oct 3, 2023 Issued
Array ( [id] => 19500518 [patent_doc_number] => 20240339536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/478215 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478215
SEMICONDUCTOR DEVICE Sep 28, 2023 Pending
Array ( [id] => 19881305 [patent_doc_number] => 20250113562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/478054 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478054 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478054
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME Sep 28, 2023 Pending
Array ( [id] => 18905978 [patent_doc_number] => 20240021463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => STAGE APPARATUS, EXPOSURE APPARATUS, INSPECTION APPARATUS, AND DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/476310 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476310
STAGE APPARATUS, EXPOSURE APPARATUS, INSPECTION APPARATUS, AND DEVICE MANUFACTURING METHOD Sep 27, 2023 Pending
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