Search

Preston Smith

Examiner (ID: 9382, Phone: (571)270-7084 , Office: P/1792 )

Most Active Art Unit
1792
Art Unit(s)
1794, 1792, 1782
Total Applications
477
Issued Applications
155
Pending Applications
9
Abandoned Applications
312

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18228002 [patent_doc_number] => 20230066996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => LATERAL BIPOLAR JUNCTION TRANSISTORS CONTAINING A TWO-DIMENSIONAL MATERIAL [patent_app_type] => utility [patent_app_number] => 17/541603 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541603
LATERAL BIPOLAR JUNCTION TRANSISTORS CONTAINING A TWO-DIMENSIONAL MATERIAL Dec 2, 2021 Pending
Array ( [id] => 17933283 [patent_doc_number] => 20220328409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => TARGETED POWER GRID STRUCTURE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/538080 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538080
TARGETED POWER GRID STRUCTURE AND METHOD Nov 29, 2021 Pending
Array ( [id] => 18977235 [patent_doc_number] => 20240057327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => THREE-DIMENSIONAL FLASH MEMORY INCLUDING CHANNEL LAYER HAVING MULTILAYER STRUCTURE, AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/260859 [patent_app_country] => US [patent_app_date] => 2021-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18260859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/260859
THREE-DIMENSIONAL FLASH MEMORY INCLUDING CHANNEL LAYER HAVING MULTILAYER STRUCTURE, AND METHOD FOR MANUFACTURING SAME Nov 24, 2021 Pending
Array ( [id] => 17764956 [patent_doc_number] => 20220238569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 17/518919 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518919
IMAGE SENSOR Nov 3, 2021 Pending
Array ( [id] => 17993162 [patent_doc_number] => 20220359199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => FIN STRUCTURE WITH REDUCED DEFECTS AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/452673 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452673
FIN STRUCTURE WITH REDUCED DEFECTS AND MANUFACTURING METHOD THEREOF Oct 27, 2021 Pending
Array ( [id] => 19487236 [patent_doc_number] => 12106960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Electric field management in semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/504391 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4701 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504391
Electric field management in semiconductor devices Oct 17, 2021 Issued
Array ( [id] => 17551758 [patent_doc_number] => 20220123100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/500313 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500313
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Oct 12, 2021 Abandoned
Array ( [id] => 18322071 [patent_doc_number] => 20230120199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => COPPER INTERCONNECTS WITH AN EMBEDDED DIELECTRIC CAP BETWEEN LINES [patent_app_type] => utility [patent_app_number] => 17/493884 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493884
COPPER INTERCONNECTS WITH AN EMBEDDED DIELECTRIC CAP BETWEEN LINES Oct 4, 2021 Pending
Array ( [id] => 17886392 [patent_doc_number] => 20220301870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/474929 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474929
SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS Sep 13, 2021 Abandoned
Array ( [id] => 18943730 [patent_doc_number] => 20240038869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => NORMALLY-OFF MESFET DEVICE WITH STACKED GATE CONTACT [patent_app_type] => utility [patent_app_number] => 18/245838 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18245838 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/245838
NORMALLY-OFF MESFET DEVICE WITH STACKED GATE CONTACT Sep 12, 2021 Pending
Array ( [id] => 17855357 [patent_doc_number] => 20220285400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => 3D MEMORY DEVICE WITH MODULATED DOPED CHANNEL [patent_app_type] => utility [patent_app_number] => 17/470826 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470826
3D memory device with modulated doped channel Sep 8, 2021 Issued
Array ( [id] => 18223973 [patent_doc_number] => 20230062967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE WITH CONTACTS HAVING DIFFERENT DIMENSIONS AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/462309 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462309
SEMICONDUCTOR DEVICE WITH CONTACTS HAVING DIFFERENT DIMENSIONS AND METHOD FOR FABRICATING THE SAME Aug 30, 2021 Abandoned
Array ( [id] => 19414878 [patent_doc_number] => 12080715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Semiconductor device with varying gate dimensions and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/407566 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 46 [patent_no_of_words] => 11352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407566
Semiconductor device with varying gate dimensions and methods of forming the same Aug 19, 2021 Issued
Array ( [id] => 17853157 [patent_doc_number] => 20220283199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => NITRIDE SEMICONDUCTOR, WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE NITRIDE SEMICONDUCTOR [patent_app_type] => utility [patent_app_number] => 17/400510 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400510 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400510
NITRIDE SEMICONDUCTOR, WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE NITRIDE SEMICONDUCTOR Aug 11, 2021 Pending
Array ( [id] => 17933374 [patent_doc_number] => 20220328500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => High Density 3 Dimensional Gate All Around Memory [patent_app_type] => utility [patent_app_number] => 17/393381 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393381
High Density 3 Dimensional Gate All Around Memory Aug 2, 2021 Pending
Array ( [id] => 17933548 [patent_doc_number] => 20220328674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/384837 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384837
Semiconductor device and method for manufacturing the same Jul 25, 2021 Issued
Array ( [id] => 17373751 [patent_doc_number] => 20220028803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => METHOD OF MAKING AN INDIVIDUALIZATION ZONE OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/443138 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443138
Method of making an individualization zone of an integrated circuit Jul 20, 2021 Issued
Array ( [id] => 17933521 [patent_doc_number] => 20220328647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => Semiconductor Devices with Air Gaps and the Method Thereof [patent_app_type] => utility [patent_app_number] => 17/380422 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380422 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380422
Semiconductor devices with air gaps and the method thereof Jul 19, 2021 Issued
Array ( [id] => 20307188 [patent_doc_number] => 12453199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Imaging device [patent_app_type] => utility [patent_app_number] => 17/370012 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7962 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370012
Imaging device Jul 7, 2021 Issued
Array ( [id] => 17360011 [patent_doc_number] => 20220020807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => INTERMEDIATE CONNECTION MEMBER, METHOD FOR MANUFACTURING INTERMEDIATE CONNECTION MEMBER, ELECTRONIC MODULE, METHOD FOR MANUFACTURING ELECTRONIC MODULE, AND ELECTRONIC EQUIPMENT [patent_app_type] => utility [patent_app_number] => 17/370982 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370982
Intermediate connection member, method for manufacturing intermediate connection member, electronic module, method for manufacturing electronic module, and electronic equipment Jul 7, 2021 Issued
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