Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
90/008977 ARTICLE COMPRISING A QUANTUM WELL LASER Dec 26, 2007 Issued
90/008947 COMMUNICATION CABLE HAVING A STRIATED CABLE JACKET Dec 9, 2007 Issued
90/008853 COMPUTER MEMORY CHIP WITH FIELD PROGRAMMABLE MEMORY CELL ARRAYS (FPMCAS), AND METHOD OF CONFIGURING Sep 23, 2007 Issued
90/010027 Radiological Image Interpretation Apparatus and Method Sep 13, 2007 Issued
90/010026 Radiological Image Interpretation Apparatus and Method Sep 13, 2007 Issued
95/000202 METHOD AND APPARATUS FOR RECEIVING A UNIVERSIAL INPUT VOLTAGE IN A WELDING PLASMA OR HEATING POWER SOURCE Jan 16, 2007 Issued
95/000204 METHOD AND APPARATUS FOR RECEIVING A UNIVERSAL INPUT VOLTAGE IN A WELDING, PLASMA OR HEATING POWER SOURCE Jan 16, 2007 Issued
95/000203 METHOD AND APPARATUS FOR RECEIVING A UNIVERSAL INPUT VOLTAGE IN A WELDING,PLASMA OR HEATING POWER SOURCE Jan 15, 2007 Issued
90/008355 WIRE MANAGEMENT GROMMET Nov 30, 2006 Issued
Array ( [id] => 425650 [patent_doc_number] => 07271633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Charge pump structure for reducing capacitance in loop filter of a phase locked loop' [patent_app_type] => utility [patent_app_number] => 11/561899 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8497 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/271/07271633.pdf [firstpage_image] =>[orig_patent_app_number] => 11561899 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561899
Charge pump structure for reducing capacitance in loop filter of a phase locked loop Nov 20, 2006 Issued
90/008156 PARALLEL PROCESSOR SYSTEM FOR PROCESSING NATURAL CONCURRENCES AND METHOD THEREFOR Oct 19, 2006 Issued
90/008228 SYSTEM FOR EXECUTING INSTRUCTIONS WITH DELAYED FIRING TIMES Sep 19, 2006 Issued
Array ( [id] => 394483 [patent_doc_number] => 07298184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit' [patent_app_type] => utility [patent_app_number] => 11/513655 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298184.pdf [firstpage_image] =>[orig_patent_app_number] => 11513655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513655
Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit Aug 30, 2006 Issued
Array ( [id] => 7603007 [patent_doc_number] => 07236027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof' [patent_app_type] => utility [patent_app_number] => 11/463897 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3849 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236027.pdf [firstpage_image] =>[orig_patent_app_number] => 11463897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463897
Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof Aug 10, 2006 Issued
Array ( [id] => 5659572 [patent_doc_number] => 20060250168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Highly configurable PLL architecture for programmable logic' [patent_app_type] => utility [patent_app_number] => 11/486565 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6138 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250168.pdf [firstpage_image] =>[orig_patent_app_number] => 11486565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486565
Highly configurable PLL architecture for programmable logic Jul 12, 2006 Issued
Array ( [id] => 920269 [patent_doc_number] => 07321250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/440073 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5810 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321250.pdf [firstpage_image] =>[orig_patent_app_number] => 11440073 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/440073
Integrated circuit device May 24, 2006 Issued
Array ( [id] => 5757835 [patent_doc_number] => 20060208780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Delay-locked loop with feedback compensation' [patent_app_type] => utility [patent_app_number] => 11/439685 [patent_app_country] => US [patent_app_date] => 2006-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20060208780.pdf [firstpage_image] =>[orig_patent_app_number] => 11439685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/439685
Delay-locked loop with feedback compensation May 23, 2006 Issued
Array ( [id] => 440551 [patent_doc_number] => 07259608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal' [patent_app_type] => utility [patent_app_number] => 11/433216 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 5859 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259608.pdf [firstpage_image] =>[orig_patent_app_number] => 11433216 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433216
System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal May 10, 2006 Issued
Array ( [id] => 448000 [patent_doc_number] => 07253672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal' [patent_app_type] => utility [patent_app_number] => 11/430471 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 6441 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253672.pdf [firstpage_image] =>[orig_patent_app_number] => 11430471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/430471
System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal May 7, 2006 Issued
Array ( [id] => 5703554 [patent_doc_number] => 20060192601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Method and apparatus for digital phase generation at high frequencies' [patent_app_type] => utility [patent_app_number] => 11/413790 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7719 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20060192601.pdf [firstpage_image] =>[orig_patent_app_number] => 11413790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/413790
Method and apparatus for digital phase generation at high frequencies Apr 27, 2006 Issued
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