![](/images/general/no_picture/200_user.png)
Qian Yang
Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )
Most Active Art Unit | 2668 |
Art Unit(s) | 2625, 2674, 2668, 2662 |
Total Applications | 1035 |
Issued Applications | 734 |
Pending Applications | 61 |
Abandoned Applications | 239 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 412164
[patent_doc_number] => 07282969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-16
[patent_title] => 'Low divide ratio programmable frequency divider and method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/380917
[patent_app_country] => US
[patent_app_date] => 2006-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6775
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/282/07282969.pdf
[firstpage_image] =>[orig_patent_app_number] => 11380917
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/380917 | Low divide ratio programmable frequency divider and method thereof | Apr 27, 2006 | Issued |
90/008014 | HIGH-EFFICIENCY ADAPTIVE DC/AC CONVERTER | Apr 18, 2006 | Issued |
Array
(
[id] => 383507
[patent_doc_number] => 07307459
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-11
[patent_title] => 'Programmable phase-locked loop circuitry for programmable logic device'
[patent_app_type] => utility
[patent_app_number] => 11/378695
[patent_app_country] => US
[patent_app_date] => 2006-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4241
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/307/07307459.pdf
[firstpage_image] =>[orig_patent_app_number] => 11378695
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/378695 | Programmable phase-locked loop circuitry for programmable logic device | Mar 15, 2006 | Issued |
Array
(
[id] => 4975224
[patent_doc_number] => 20070216454
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'FAST LOCKING MECHANISM FOR DELAY LOCK LOOPS AND PHASE LOCK LOOPS'
[patent_app_type] => utility
[patent_app_number] => 11/374808
[patent_app_country] => US
[patent_app_date] => 2006-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4731
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20070216454.pdf
[firstpage_image] =>[orig_patent_app_number] => 11374808
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/374808 | Fast locking mechanism for delay lock loops and phase lock loops | Mar 13, 2006 | Issued |
Array
(
[id] => 5869806
[patent_doc_number] => 20060164127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'High speed peak amplitude comparator'
[patent_app_type] => utility
[patent_app_number] => 11/369604
[patent_app_country] => US
[patent_app_date] => 2006-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2546
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20060164127.pdf
[firstpage_image] =>[orig_patent_app_number] => 11369604
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/369604 | High speed peak amplitude comparator | Mar 5, 2006 | Abandoned |
90/007922 | PARELLEL PROCESSOR SYSTEM FOR PROCESSING NATURAL CONCURRENCIES AND METHOD THEREFOR | Feb 8, 2006 | Issued |
Array
(
[id] => 504362
[patent_doc_number] => 07205802
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-04-17
[patent_title] => 'Apparatus and method for controlling a delay chain'
[patent_app_type] => utility
[patent_app_number] => 11/349516
[patent_app_country] => US
[patent_app_date] => 2006-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 4015
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205802.pdf
[firstpage_image] =>[orig_patent_app_number] => 11349516
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/349516 | Apparatus and method for controlling a delay chain | Feb 2, 2006 | Issued |
Array
(
[id] => 5665118
[patent_doc_number] => 20060170468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'PLL circuit and program for same'
[patent_app_type] => utility
[patent_app_number] => 11/340633
[patent_app_country] => US
[patent_app_date] => 2006-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 9027
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20060170468.pdf
[firstpage_image] =>[orig_patent_app_number] => 11340633
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/340633 | PLL circuit and program for same | Jan 26, 2006 | Issued |
Array
(
[id] => 5175593
[patent_doc_number] => 20070176651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-02
[patent_title] => 'Circuits for locally generating non-integral divided clocks with centralized state machines'
[patent_app_type] => utility
[patent_app_number] => 11/341032
[patent_app_country] => US
[patent_app_date] => 2006-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 2960
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0176/20070176651.pdf
[firstpage_image] =>[orig_patent_app_number] => 11341032
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/341032 | Circuits for locally generating non-integral divided clocks with centralized state machines | Jan 26, 2006 | Issued |
Array
(
[id] => 7603001
[patent_doc_number] => 07236033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-26
[patent_title] => 'System and method for detecting processing speed of integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/340755
[patent_app_country] => US
[patent_app_date] => 2006-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 4269
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/236/07236033.pdf
[firstpage_image] =>[orig_patent_app_number] => 11340755
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/340755 | System and method for detecting processing speed of integrated circuit | Jan 26, 2006 | Issued |
Array
(
[id] => 918698
[patent_doc_number] => 07323915
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-29
[patent_title] => 'Delay locked loop with selectable delay'
[patent_app_type] => utility
[patent_app_number] => 11/335749
[patent_app_country] => US
[patent_app_date] => 2006-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7427
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/323/07323915.pdf
[firstpage_image] =>[orig_patent_app_number] => 11335749
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/335749 | Delay locked loop with selectable delay | Jan 18, 2006 | Issued |
Array
(
[id] => 5665108
[patent_doc_number] => 20060170458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Output buffer with improved slew rate and method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/319232
[patent_app_country] => US
[patent_app_date] => 2005-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5268
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20060170458.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319232
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319232 | Output buffer with improved slew rate and method thereof | Dec 27, 2005 | Issued |
Array
(
[id] => 5020069
[patent_doc_number] => 20070146035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Receive clock deskewing method, apparatus, and system'
[patent_app_type] => utility
[patent_app_number] => 11/319689
[patent_app_country] => US
[patent_app_date] => 2005-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3448
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20070146035.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319689
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319689 | Receive clock deskewing method, apparatus, and system | Dec 27, 2005 | Issued |
Array
(
[id] => 509201
[patent_doc_number] => 07202716
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-04-10
[patent_title] => 'Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domain'
[patent_app_type] => utility
[patent_app_number] => 11/320254
[patent_app_country] => US
[patent_app_date] => 2005-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4996
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/202/07202716.pdf
[firstpage_image] =>[orig_patent_app_number] => 11320254
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/320254 | Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domain | Dec 26, 2005 | Issued |
Array
(
[id] => 5054788
[patent_doc_number] => 20070057709
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-15
[patent_title] => 'Clock generation circuit and clock generation method'
[patent_app_type] => utility
[patent_app_number] => 11/312392
[patent_app_country] => US
[patent_app_date] => 2005-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7325
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20070057709.pdf
[firstpage_image] =>[orig_patent_app_number] => 11312392
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/312392 | Clock generation circuit and clock generation method | Dec 20, 2005 | Issued |
Array
(
[id] => 496864
[patent_doc_number] => 07212049
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-01
[patent_title] => 'Digital-control-type phase-composing circuit system'
[patent_app_type] => utility
[patent_app_number] => 11/305037
[patent_app_country] => US
[patent_app_date] => 2005-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2208
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/212/07212049.pdf
[firstpage_image] =>[orig_patent_app_number] => 11305037
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/305037 | Digital-control-type phase-composing circuit system | Dec 18, 2005 | Issued |
Array
(
[id] => 5805569
[patent_doc_number] => 20060091922
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Duty cycle correction'
[patent_app_type] => utility
[patent_app_number] => 11/300073
[patent_app_country] => US
[patent_app_date] => 2005-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4991
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20060091922.pdf
[firstpage_image] =>[orig_patent_app_number] => 11300073
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/300073 | Duty cycle correction | Dec 13, 2005 | Issued |
Array
(
[id] => 500714
[patent_doc_number] => 07208986
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-24
[patent_title] => 'Measure-controlled delay circuits with reduced phase error'
[patent_app_type] => utility
[patent_app_number] => 11/293634
[patent_app_country] => US
[patent_app_date] => 2005-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5871
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/208/07208986.pdf
[firstpage_image] =>[orig_patent_app_number] => 11293634
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/293634 | Measure-controlled delay circuits with reduced phase error | Dec 1, 2005 | Issued |
90/007811 | PRECISION OPTICAL MOUNTS | Nov 22, 2005 | Issued |
Array
(
[id] => 425651
[patent_doc_number] => 07271634
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-09-18
[patent_title] => 'Delay-locked loop having a plurality of lock modes'
[patent_app_type] => utility
[patent_app_number] => 11/286454
[patent_app_country] => US
[patent_app_date] => 2005-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 7816
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/271/07271634.pdf
[firstpage_image] =>[orig_patent_app_number] => 11286454
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/286454 | Delay-locked loop having a plurality of lock modes | Nov 22, 2005 | Issued |