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Qian Yang
Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )
Most Active Art Unit | 2668 |
Art Unit(s) | 2625, 2674, 2668, 2662 |
Total Applications | 1035 |
Issued Applications | 734 |
Pending Applications | 61 |
Abandoned Applications | 239 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
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[patent_doc_number] => 07215165
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[patent_kind] => B2
[patent_issue_date] => 2007-05-08
[patent_title] => 'Clock generating circuit and clock generating method'
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[patent_app_number] => 11/267152
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[pdf_file] => patents/07/215/07215165.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/267152 | Clock generating circuit and clock generating method | Nov 6, 2005 | Issued |
90/007791 | MEDICAL X-RAY DIGITIZING AND CHART STORAGE SYSTEM | Oct 30, 2005 | Issued |
Array
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[patent_title] => 'Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronization'
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[patent_app_number] => 11/257258
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Array
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[patent_title] => 'Semiconductor integrated circuit having built-in PLL circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/241995 | Semiconductor integrated circuit having built-in PLL circuit | Oct 3, 2005 | Issued |
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[patent_title] => 'Configurable circuit structure having reduced susceptibility to interference when using at least two such circuits to perform like functions'
[patent_app_type] => utility
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[patent_title] => 'Skew tolerant phase shift driver with controlled reset pulse width'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/235646 | Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme | Sep 25, 2005 | Issued |
Array
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[patent_title] => 'Charge pump circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/234379 | Charge pump circuit | Sep 25, 2005 | Abandoned |
Array
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[patent_doc_number] => 20060290392
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[patent_issue_date] => 2006-12-28
[patent_title] => 'Clock generators'
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[firstpage_image] =>[orig_patent_app_number] => 11232949
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/232949 | Programmable fractional-N clock generators | Sep 22, 2005 | Issued |
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/232840 | Matched current delay cell and delay locked loop | Sep 20, 2005 | Issued |
Array
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[patent_title] => 'Delay locked loop structure providing first and second locked clock signals'
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