Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 470093 [patent_doc_number] => 07233182 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-19 [patent_title] => 'Circuitry for eliminating false lock in delay-locked loops' [patent_app_type] => utility [patent_app_number] => 11/169957 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4586 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/233/07233182.pdf [firstpage_image] =>[orig_patent_app_number] => 11169957 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169957
Circuitry for eliminating false lock in delay-locked loops Jun 27, 2005 Issued
Array ( [id] => 5600046 [patent_doc_number] => 20060290391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Integrated clock generator with programmable spread spectrum using standard PLL circuitry' [patent_app_type] => utility [patent_app_number] => 11/167629 [patent_app_country] => US [patent_app_date] => 2005-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2078 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20060290391.pdf [firstpage_image] =>[orig_patent_app_number] => 11167629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/167629
Integrated clock generator with programmable spread spectrum using standard PLL circuitry Jun 26, 2005 Issued
Array ( [id] => 444170 [patent_doc_number] => 07256646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Neutralization techniques for differential low noise amplifiers' [patent_app_type] => utility [patent_app_number] => 11/157246 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7502 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256646.pdf [firstpage_image] =>[orig_patent_app_number] => 11157246 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157246
Neutralization techniques for differential low noise amplifiers Jun 20, 2005 Issued
Array ( [id] => 6975934 [patent_doc_number] => 20050285649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Duty cycle correction circuit for use in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/147629 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3122 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285649.pdf [firstpage_image] =>[orig_patent_app_number] => 11147629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/147629
Duty cycle correction circuit for use in a semiconductor device Jun 7, 2005 Issued
Array ( [id] => 7054266 [patent_doc_number] => 20050275438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Capacitance multiplier with enhanced gain and low power consumption' [patent_app_type] => utility [patent_app_number] => 11/145254 [patent_app_country] => US [patent_app_date] => 2005-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20050275438.pdf [firstpage_image] =>[orig_patent_app_number] => 11145254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/145254
Capacitance multiplier with enhanced gain and low power consumption Jun 2, 2005 Issued
Array ( [id] => 5629272 [patent_doc_number] => 20060145740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'VCDL-based dual loop DLL having infinite phase shift function' [patent_app_type] => utility [patent_app_number] => 11/142698 [patent_app_country] => US [patent_app_date] => 2005-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6945 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145740.pdf [firstpage_image] =>[orig_patent_app_number] => 11142698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/142698
VCDL-based dual loop DLL having infinite phase shift function May 31, 2005 Issued
Array ( [id] => 504420 [patent_doc_number] => 07205813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Differential type delay cells and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 11/141568 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4687 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205813.pdf [firstpage_image] =>[orig_patent_app_number] => 11141568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/141568
Differential type delay cells and methods of operating the same May 30, 2005 Issued
Array ( [id] => 5606129 [patent_doc_number] => 20060267645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'System and method for reducing transient response in a fractional N phase lock loop' [patent_app_type] => utility [patent_app_number] => 11/139160 [patent_app_country] => US [patent_app_date] => 2005-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2094 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20060267645.pdf [firstpage_image] =>[orig_patent_app_number] => 11139160 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/139160
System and method for reducing transient response in a fractional N phase lock loop May 27, 2005 Issued
Array ( [id] => 683271 [patent_doc_number] => 07081782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Locked loop with dual rail regulation' [patent_app_type] => utility [patent_app_number] => 11/130682 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 17594 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081782.pdf [firstpage_image] =>[orig_patent_app_number] => 11130682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/130682
Locked loop with dual rail regulation May 16, 2005 Issued
Array ( [id] => 696666 [patent_doc_number] => 07071743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Programmable phase-locked loop circuitry for programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/130079 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4218 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071743.pdf [firstpage_image] =>[orig_patent_app_number] => 11130079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/130079
Programmable phase-locked loop circuitry for programmable logic device May 15, 2005 Issued
Array ( [id] => 401840 [patent_doc_number] => 07292077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-06 [patent_title] => 'Phase-lock loop and loop filter thereof' [patent_app_type] => utility [patent_app_number] => 11/122657 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3585 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/292/07292077.pdf [firstpage_image] =>[orig_patent_app_number] => 11122657 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/122657
Phase-lock loop and loop filter thereof May 3, 2005 Issued
Array ( [id] => 7177824 [patent_doc_number] => 20050189971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'System with dual rail regulated locked loop' [patent_app_type] => utility [patent_app_number] => 11/114433 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 31374 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20050189971.pdf [firstpage_image] =>[orig_patent_app_number] => 11114433 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/114433
System with dual rail regulated locked loop Apr 25, 2005 Issued
Array ( [id] => 422302 [patent_doc_number] => 07274236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Variable delay line with multiple hierarchy' [patent_app_type] => utility [patent_app_number] => 11/107587 [patent_app_country] => US [patent_app_date] => 2005-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3401 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274236.pdf [firstpage_image] =>[orig_patent_app_number] => 11107587 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/107587
Variable delay line with multiple hierarchy Apr 14, 2005 Issued
Array ( [id] => 5854948 [patent_doc_number] => 20060226881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Sampling phase detector for delay-locked loop' [patent_app_type] => utility [patent_app_number] => 11/103527 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20060226881.pdf [firstpage_image] =>[orig_patent_app_number] => 11103527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/103527
Sampling phase detector for delay-locked loop Apr 11, 2005 Issued
Array ( [id] => 5751572 [patent_doc_number] => 20060220721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Clock delay compensation circuit' [patent_app_type] => utility [patent_app_number] => 11/098106 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220721.pdf [firstpage_image] =>[orig_patent_app_number] => 11098106 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/098106
Clock delay compensation circuit Apr 3, 2005 Issued
Array ( [id] => 488134 [patent_doc_number] => 07218164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Emitter switching driving network to control the storage time' [patent_app_type] => utility [patent_app_number] => 11/097442 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 6024 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218164.pdf [firstpage_image] =>[orig_patent_app_number] => 11097442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097442
Emitter switching driving network to control the storage time Mar 30, 2005 Issued
Array ( [id] => 5629274 [patent_doc_number] => 20060145742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Pulse-on-edge circuit' [patent_app_type] => utility [patent_app_number] => 11/095238 [patent_app_country] => US [patent_app_date] => 2005-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145742.pdf [firstpage_image] =>[orig_patent_app_number] => 11095238 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095238
Pulse-on-edge circuit Mar 29, 2005 Issued
Array ( [id] => 509136 [patent_doc_number] => 07202709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Waveform output device and drive device' [patent_app_type] => utility [patent_app_number] => 11/088894 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4111 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202709.pdf [firstpage_image] =>[orig_patent_app_number] => 11088894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088894
Waveform output device and drive device Mar 24, 2005 Issued
Array ( [id] => 5698022 [patent_doc_number] => 20060214706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Reduced phase noise frequency divider' [patent_app_type] => utility [patent_app_number] => 11/090525 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1308 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214706.pdf [firstpage_image] =>[orig_patent_app_number] => 11090525 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/090525
Reduced phase noise frequency divider Mar 24, 2005 Abandoned
Array ( [id] => 474491 [patent_doc_number] => 07230467 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Constant edge generation circuits and methods and systems using the same' [patent_app_type] => utility [patent_app_number] => 11/089145 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230467.pdf [firstpage_image] =>[orig_patent_app_number] => 11089145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089145
Constant edge generation circuits and methods and systems using the same Mar 23, 2005 Issued
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