Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 681517 [patent_doc_number] => 07084681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'PLL lock detection circuit using edge detection and a state machine' [patent_app_type] => utility [patent_app_number] => 11/088152 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4757 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084681.pdf [firstpage_image] =>[orig_patent_app_number] => 11088152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088152
PLL lock detection circuit using edge detection and a state machine Mar 22, 2005 Issued
Array ( [id] => 398258 [patent_doc_number] => 07295049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method and circuit for rapid alignment of signals' [patent_app_type] => utility [patent_app_number] => 11/088028 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4489 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295049.pdf [firstpage_image] =>[orig_patent_app_number] => 11088028 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088028
Method and circuit for rapid alignment of signals Mar 21, 2005 Issued
Array ( [id] => 7002979 [patent_doc_number] => 20050168292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Leakage compensation for capacitors in loop filters' [patent_app_type] => utility [patent_app_number] => 11/084438 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5241 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20050168292.pdf [firstpage_image] =>[orig_patent_app_number] => 11084438 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/084438
Leakage compensation for capacitors in loop filters Mar 16, 2005 Issued
Array ( [id] => 627513 [patent_doc_number] => 07135900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Phase locked loop with adaptive loop bandwidth' [patent_app_type] => utility [patent_app_number] => 11/082497 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13980 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135900.pdf [firstpage_image] =>[orig_patent_app_number] => 11082497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082497
Phase locked loop with adaptive loop bandwidth Mar 16, 2005 Issued
Array ( [id] => 532224 [patent_doc_number] => 07183823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, and a switch mode power converter' [patent_app_type] => utility [patent_app_number] => 11/080882 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2787 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183823.pdf [firstpage_image] =>[orig_patent_app_number] => 11080882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080882
Method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, and a switch mode power converter Mar 14, 2005 Issued
Array ( [id] => 638854 [patent_doc_number] => 07126401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device' [patent_app_type] => utility [patent_app_number] => 11/077374 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7006 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126401.pdf [firstpage_image] =>[orig_patent_app_number] => 11077374 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/077374
Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device Mar 10, 2005 Issued
Array ( [id] => 730859 [patent_doc_number] => 07042255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-09 [patent_title] => 'Programmable differential capacitance for equalization circuits' [patent_app_type] => utility [patent_app_number] => 11/075368 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4151 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042255.pdf [firstpage_image] =>[orig_patent_app_number] => 11075368 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/075368
Programmable differential capacitance for equalization circuits Mar 7, 2005 Issued
Array ( [id] => 873794 [patent_doc_number] => 07362152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Apparatus and method for digital phase control of a pulse width modulation generator for microprocessor/DSP in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/071027 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2567 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362152.pdf [firstpage_image] =>[orig_patent_app_number] => 11071027 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071027
Apparatus and method for digital phase control of a pulse width modulation generator for microprocessor/DSP in integrated circuits Mar 2, 2005 Issued
Array ( [id] => 7048945 [patent_doc_number] => 20050184832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Symmetric microwave filter and microwave integrated circuit merging the same' [patent_app_type] => utility [patent_app_number] => 11/064003 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14740 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184832.pdf [firstpage_image] =>[orig_patent_app_number] => 11064003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064003
Symmetric microwave filter and microwave integrated circuit merging the same Feb 23, 2005 Issued
Array ( [id] => 775120 [patent_doc_number] => 07002390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Delay matching for clock distribution in a logic circuit' [patent_app_type] => utility [patent_app_number] => 11/053167 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4376 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002390.pdf [firstpage_image] =>[orig_patent_app_number] => 11053167 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/053167
Delay matching for clock distribution in a logic circuit Feb 6, 2005 Issued
Array ( [id] => 735166 [patent_doc_number] => 07038517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Timing vernier using a delay locked loop' [patent_app_type] => utility [patent_app_number] => 11/037365 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038517.pdf [firstpage_image] =>[orig_patent_app_number] => 11037365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037365
Timing vernier using a delay locked loop Jan 18, 2005 Issued
Array ( [id] => 7169972 [patent_doc_number] => 20050122137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'High speed peak amplitude comparator' [patent_app_type] => utility [patent_app_number] => 11/031102 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122137.pdf [firstpage_image] =>[orig_patent_app_number] => 11031102 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/031102
High speed peak amplitude comparator Jan 5, 2005 Issued
Array ( [id] => 785964 [patent_doc_number] => 06989697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Non-quasistatic phase lock loop frequency divider circuit' [patent_app_type] => utility [patent_app_number] => 11/030345 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6626 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989697.pdf [firstpage_image] =>[orig_patent_app_number] => 11030345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030345
Non-quasistatic phase lock loop frequency divider circuit Jan 5, 2005 Issued
Array ( [id] => 5629262 [patent_doc_number] => 20060145730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Signal processing apparatus having internal clock signal source' [patent_app_type] => utility [patent_app_number] => 11/026654 [patent_app_country] => US [patent_app_date] => 2004-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145730.pdf [firstpage_image] =>[orig_patent_app_number] => 11026654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026654
Signal processing apparatus having internal clock signal source Dec 30, 2004 Issued
Array ( [id] => 5629270 [patent_doc_number] => 20060145738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method and circuit configuration for synchronous resetting of a multiple clock domain circuit' [patent_app_type] => utility [patent_app_number] => 11/027906 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2706 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145738.pdf [firstpage_image] =>[orig_patent_app_number] => 11027906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027906
Method and circuit configuration for synchronous resetting of a multiple clock domain circuit Dec 29, 2004 Issued
Array ( [id] => 5653341 [patent_doc_number] => 20060139076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Z-state circuit for delay-locked loops' [patent_app_type] => utility [patent_app_number] => 11/024542 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139076.pdf [firstpage_image] =>[orig_patent_app_number] => 11024542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024542
Z-state circuit for delay-locked loops Dec 27, 2004 Abandoned
Array ( [id] => 613330 [patent_doc_number] => 07148730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Z-state circuit for phase-locked loops' [patent_app_type] => utility [patent_app_number] => 11/023683 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148730.pdf [firstpage_image] =>[orig_patent_app_number] => 11023683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/023683
Z-state circuit for phase-locked loops Dec 26, 2004 Issued
Array ( [id] => 394487 [patent_doc_number] => 07298188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Timing adjustment circuit and memory controller' [patent_app_type] => utility [patent_app_number] => 11/020418 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298188.pdf [firstpage_image] =>[orig_patent_app_number] => 11020418 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020418
Timing adjustment circuit and memory controller Dec 26, 2004 Issued
Array ( [id] => 5653340 [patent_doc_number] => 20060139075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Delay locked loop using synchronous mirror delay' [patent_app_type] => utility [patent_app_number] => 11/021370 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8766 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139075.pdf [firstpage_image] =>[orig_patent_app_number] => 11021370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021370
Delay locked loop using synchronous mirror delay Dec 22, 2004 Issued
Array ( [id] => 540519 [patent_doc_number] => 07173459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Trimming method and apparatus for voltage controlled delay loop with central interpolator' [patent_app_type] => utility [patent_app_number] => 11/020022 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173459.pdf [firstpage_image] =>[orig_patent_app_number] => 11020022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020022
Trimming method and apparatus for voltage controlled delay loop with central interpolator Dec 21, 2004 Issued
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