Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7239231 [patent_doc_number] => 20050140408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Delay locked loop in semiconductor memory device and locking method thereof' [patent_app_type] => utility [patent_app_number] => 11/017644 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1842 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140408.pdf [firstpage_image] =>[orig_patent_app_number] => 11017644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/017644
Delay locked loop in semiconductor memory device and locking method thereof Dec 21, 2004 Issued
Array ( [id] => 562551 [patent_doc_number] => 07161397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Digital delay locked loop capable of correcting duty cycle and its method' [patent_app_type] => utility [patent_app_number] => 11/020491 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4777 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161397.pdf [firstpage_image] =>[orig_patent_app_number] => 11020491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020491
Digital delay locked loop capable of correcting duty cycle and its method Dec 20, 2004 Issued
Array ( [id] => 523778 [patent_doc_number] => 07190196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-13 [patent_title] => 'Dual-edge synchronized data sampler' [patent_app_type] => utility [patent_app_number] => 11/015322 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5957 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190196.pdf [firstpage_image] =>[orig_patent_app_number] => 11015322 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015322
Dual-edge synchronized data sampler Dec 16, 2004 Issued
Array ( [id] => 638850 [patent_doc_number] => 07126400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Delay adjustment circuit, integrated circuit device, and delay adjustment method' [patent_app_type] => utility [patent_app_number] => 11/013472 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 11139 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126400.pdf [firstpage_image] =>[orig_patent_app_number] => 11013472 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013472
Delay adjustment circuit, integrated circuit device, and delay adjustment method Dec 16, 2004 Issued
Array ( [id] => 624130 [patent_doc_number] => 07138841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-21 [patent_title] => 'Programmable phase shift and duty cycle correction circuit and method' [patent_app_type] => utility [patent_app_number] => 11/014578 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7223 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138841.pdf [firstpage_image] =>[orig_patent_app_number] => 11014578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/014578
Programmable phase shift and duty cycle correction circuit and method Dec 15, 2004 Issued
Array ( [id] => 6994575 [patent_doc_number] => 20050134353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Semiconductor integrated circuit and manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/012724 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4798 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134353.pdf [firstpage_image] =>[orig_patent_app_number] => 11012724 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012724
Semiconductor integrated circuit and manufacturing method Dec 15, 2004 Issued
Array ( [id] => 785980 [patent_doc_number] => 06989704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Delay circuit having function of filter circuit' [patent_app_type] => utility [patent_app_number] => 11/010290 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5254 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989704.pdf [firstpage_image] =>[orig_patent_app_number] => 11010290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/010290
Delay circuit having function of filter circuit Dec 13, 2004 Issued
Array ( [id] => 683274 [patent_doc_number] => 07081784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Data output circuit of memory device' [patent_app_type] => utility [patent_app_number] => 11/008254 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1752 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081784.pdf [firstpage_image] =>[orig_patent_app_number] => 11008254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008254
Data output circuit of memory device Dec 9, 2004 Issued
Array ( [id] => 542014 [patent_doc_number] => 07176733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'High output impedance charge pump for PLL/DLL' [patent_app_type] => utility [patent_app_number] => 11/009534 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5949 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176733.pdf [firstpage_image] =>[orig_patent_app_number] => 11009534 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009534
High output impedance charge pump for PLL/DLL Dec 9, 2004 Issued
Array ( [id] => 5909831 [patent_doc_number] => 20060125534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Zero idle time Z-state circuit for phase-locked loops, delay-locked loops, and switching regulators' [patent_app_type] => utility [patent_app_number] => 11/009648 [patent_app_country] => US [patent_app_date] => 2004-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20060125534.pdf [firstpage_image] =>[orig_patent_app_number] => 11009648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009648
Zero idle time Z-state circuit for phase-locked loops, delay-locked loops, and switching regulators Dec 8, 2004 Issued
Array ( [id] => 7172562 [patent_doc_number] => 20050122820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor devices including an external power voltage control function and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 11/005523 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9164 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122820.pdf [firstpage_image] =>[orig_patent_app_number] => 11005523 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/005523
Semiconductor devices including an external power voltage control function and methods of operating the same Dec 5, 2004 Issued
Array ( [id] => 5838913 [patent_doc_number] => 20060119396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Skew tolerant high-speed digital phase detector' [patent_app_type] => utility [patent_app_number] => 11/003117 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3905 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119396.pdf [firstpage_image] =>[orig_patent_app_number] => 11003117 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003117
Skew tolerant high-speed digital phase detector Dec 2, 2004 Issued
Array ( [id] => 5838914 [patent_doc_number] => 20060119397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Apparatus and method for accurately tuning the speed of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/002548 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119397.pdf [firstpage_image] =>[orig_patent_app_number] => 11002548 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002548
Apparatus and method for accurately tuning the speed of an integrated circuit Dec 1, 2004 Issued
Array ( [id] => 6994565 [patent_doc_number] => 20050134343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'PWM signal generator' [patent_app_type] => utility [patent_app_number] => 10/998992 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4238 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134343.pdf [firstpage_image] =>[orig_patent_app_number] => 10998992 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998992
PWM signal generator Nov 29, 2004 Issued
Array ( [id] => 5612119 [patent_doc_number] => 20060114045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Voltage controlled delay loop with central interpolator' [patent_app_type] => utility [patent_app_number] => 10/999889 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2488 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20060114045.pdf [firstpage_image] =>[orig_patent_app_number] => 10999889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999889
Voltage controlled delay loop with central interpolator Nov 29, 2004 Issued
Array ( [id] => 634986 [patent_doc_number] => 07129757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Clock frequency detect with programmable jitter tolerance' [patent_app_type] => utility [patent_app_number] => 11/000439 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6443 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129757.pdf [firstpage_image] =>[orig_patent_app_number] => 11000439 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000439
Clock frequency detect with programmable jitter tolerance Nov 29, 2004 Issued
Array ( [id] => 638832 [patent_doc_number] => 07126392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Semiconductor integrated device having reduced jitter and reduced current consumption' [patent_app_type] => utility [patent_app_number] => 10/999365 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5255 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126392.pdf [firstpage_image] =>[orig_patent_app_number] => 10999365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999365
Semiconductor integrated device having reduced jitter and reduced current consumption Nov 28, 2004 Issued
Array ( [id] => 477168 [patent_doc_number] => 07227393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-05 [patent_title] => 'Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters' [patent_app_type] => utility [patent_app_number] => 10/997236 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3854 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227393.pdf [firstpage_image] =>[orig_patent_app_number] => 10997236 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997236
Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters Nov 23, 2004 Issued
Array ( [id] => 549859 [patent_doc_number] => 07164303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Delay circuit, ferroelectric memory device and electronic equipment' [patent_app_type] => utility [patent_app_number] => 10/997820 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5340 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164303.pdf [firstpage_image] =>[orig_patent_app_number] => 10997820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997820
Delay circuit, ferroelectric memory device and electronic equipment Nov 23, 2004 Issued
Array ( [id] => 6956254 [patent_doc_number] => 20050212624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Microwave circuit' [patent_app_type] => utility [patent_app_number] => 10/988152 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1641 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20050212624.pdf [firstpage_image] =>[orig_patent_app_number] => 10988152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/988152
Microwave circuit Nov 11, 2004 Issued
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