Qian Yang
Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )
Most Active Art Unit | 2668 |
Art Unit(s) | 2625, 2674, 2668, 2662 |
Total Applications | 1035 |
Issued Applications | 734 |
Pending Applications | 61 |
Abandoned Applications | 239 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 504377
[patent_doc_number] => 07205805
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-04-17
[patent_title] => 'Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error'
[patent_app_type] => utility
[patent_app_number] => 10/980676
[patent_app_country] => US
[patent_app_date] => 2004-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 5026
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205805.pdf
[firstpage_image] =>[orig_patent_app_number] => 10980676
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/980676 | Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error | Nov 1, 2004 | Issued |
Array
(
[id] => 6916038
[patent_doc_number] => 20050093599
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Delayed locked loops and methods of driving the same'
[patent_app_type] => utility
[patent_app_number] => 10/978623
[patent_app_country] => US
[patent_app_date] => 2004-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2687
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20050093599.pdf
[firstpage_image] =>[orig_patent_app_number] => 10978623
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/978623 | Delayed locked loops and methods of driving the same | Oct 31, 2004 | Issued |
Array
(
[id] => 709124
[patent_doc_number] => 07061277
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-06-13
[patent_title] => 'Low power differential-to-single-ended converter with good duty cycle performance'
[patent_app_type] => utility
[patent_app_number] => 10/972744
[patent_app_country] => US
[patent_app_date] => 2004-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2897
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/061/07061277.pdf
[firstpage_image] =>[orig_patent_app_number] => 10972744
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/972744 | Low power differential-to-single-ended converter with good duty cycle performance | Oct 24, 2004 | Issued |
Array
(
[id] => 541940
[patent_doc_number] => 07176726
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Integrated loss of signal detection with wide threshold range and precise hysteresis'
[patent_app_type] => utility
[patent_app_number] => 10/967037
[patent_app_country] => US
[patent_app_date] => 2004-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 1657
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/176/07176726.pdf
[firstpage_image] =>[orig_patent_app_number] => 10967037
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/967037 | Integrated loss of signal detection with wide threshold range and precise hysteresis | Oct 14, 2004 | Issued |
Array
(
[id] => 504432
[patent_doc_number] => 07205815
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Method and integrated circuit apparatus for reducing simultaneously switching output'
[patent_app_type] => utility
[patent_app_number] => 10/963532
[patent_app_country] => US
[patent_app_date] => 2004-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2240
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205815.pdf
[firstpage_image] =>[orig_patent_app_number] => 10963532
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/963532 | Method and integrated circuit apparatus for reducing simultaneously switching output | Oct 13, 2004 | Issued |
Array
(
[id] => 5713630
[patent_doc_number] => 20060076993
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-13
[patent_title] => 'High speed clock and data recovery system'
[patent_app_type] => utility
[patent_app_number] => 10/961201
[patent_app_country] => US
[patent_app_date] => 2004-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7935
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20060076993.pdf
[firstpage_image] =>[orig_patent_app_number] => 10961201
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/961201 | High speed clock and data recovery system | Oct 11, 2004 | Issued |
Array
(
[id] => 7243977
[patent_doc_number] => 20050073343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof'
[patent_app_type] => utility
[patent_app_number] => 10/960367
[patent_app_country] => US
[patent_app_date] => 2004-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7800
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20050073343.pdf
[firstpage_image] =>[orig_patent_app_number] => 10960367
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/960367 | Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof | Oct 5, 2004 | Issued |
Array
(
[id] => 7607010
[patent_doc_number] => 07098706
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-08-29
[patent_title] => 'High speed synchronizer for simultaneously initializing rising edge triggered and falling edge triggered flip-flops'
[patent_app_type] => utility
[patent_app_number] => 10/959573
[patent_app_country] => US
[patent_app_date] => 2004-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 42
[patent_no_of_words] => 5378
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/098/07098706.pdf
[firstpage_image] =>[orig_patent_app_number] => 10959573
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/959573 | High speed synchronizer for simultaneously initializing rising edge triggered and falling edge triggered flip-flops | Oct 5, 2004 | Issued |
Array
(
[id] => 7222591
[patent_doc_number] => 20050077943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 10/958466
[patent_app_country] => US
[patent_app_date] => 2004-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8019
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20050077943.pdf
[firstpage_image] =>[orig_patent_app_number] => 10958466
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/958466 | Semiconductor integrated circuit | Oct 5, 2004 | Issued |
Array
(
[id] => 656221
[patent_doc_number] => 07109773
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Flexible blender'
[patent_app_type] => utility
[patent_app_number] => 10/957803
[patent_app_country] => US
[patent_app_date] => 2004-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4412
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/109/07109773.pdf
[firstpage_image] =>[orig_patent_app_number] => 10957803
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/957803 | Flexible blender | Oct 3, 2004 | Issued |
Array
(
[id] => 613328
[patent_doc_number] => 07148728
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-12
[patent_title] => 'Digital delay device, digital oscillator clock signal generator and memory interface'
[patent_app_type] => utility
[patent_app_number] => 10/957211
[patent_app_country] => US
[patent_app_date] => 2004-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6453
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/148/07148728.pdf
[firstpage_image] =>[orig_patent_app_number] => 10957211
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/957211 | Digital delay device, digital oscillator clock signal generator and memory interface | Sep 30, 2004 | Issued |
Array
(
[id] => 643175
[patent_doc_number] => 07123064
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-17
[patent_title] => 'Digital phase shift circuits'
[patent_app_type] => utility
[patent_app_number] => 10/956848
[patent_app_country] => US
[patent_app_date] => 2004-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 11411
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/123/07123064.pdf
[firstpage_image] =>[orig_patent_app_number] => 10956848
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/956848 | Digital phase shift circuits | Sep 30, 2004 | Issued |
Array
(
[id] => 627510
[patent_doc_number] => 07135897
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-14
[patent_title] => 'Clock resynchronizer'
[patent_app_type] => utility
[patent_app_number] => 10/944938
[patent_app_country] => US
[patent_app_date] => 2004-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10488
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/135/07135897.pdf
[firstpage_image] =>[orig_patent_app_number] => 10944938
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/944938 | Clock resynchronizer | Sep 20, 2004 | Issued |
Array
(
[id] => 7193158
[patent_doc_number] => 20050040891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'System and method for a programmable gain amplifier'
[patent_app_type] => utility
[patent_app_number] => 10/944007
[patent_app_country] => US
[patent_app_date] => 2004-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5442
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20050040891.pdf
[firstpage_image] =>[orig_patent_app_number] => 10944007
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/944007 | System and method for a programmable gain amplifier | Sep 19, 2004 | Issued |
Array
(
[id] => 935799
[patent_doc_number] => 06975149
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-13
[patent_title] => 'Method and circuit for adjusting the timing of output data based on an operational mode of output drivers'
[patent_app_type] => utility
[patent_app_number] => 10/944136
[patent_app_country] => US
[patent_app_date] => 2004-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8469
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/975/06975149.pdf
[firstpage_image] =>[orig_patent_app_number] => 10944136
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/944136 | Method and circuit for adjusting the timing of output data based on an operational mode of output drivers | Sep 15, 2004 | Issued |
Array
(
[id] => 979522
[patent_doc_number] => 06930528
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Delay circuit and method with delay relatively independent of process, voltage, and temperature variations'
[patent_app_type] => utility
[patent_app_number] => 10/938956
[patent_app_country] => US
[patent_app_date] => 2004-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4656
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/930/06930528.pdf
[firstpage_image] =>[orig_patent_app_number] => 10938956
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/938956 | Delay circuit and method with delay relatively independent of process, voltage, and temperature variations | Sep 12, 2004 | Issued |
Array
(
[id] => 646739
[patent_doc_number] => 07119589
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-10
[patent_title] => 'Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/711313
[patent_app_country] => US
[patent_app_date] => 2004-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3962
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/119/07119589.pdf
[firstpage_image] =>[orig_patent_app_number] => 10711313
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711313 | Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof | Sep 9, 2004 | Issued |
Array
(
[id] => 681523
[patent_doc_number] => 07084685
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Method and related apparatus for outputting clock through a data path'
[patent_app_type] => utility
[patent_app_number] => 10/711254
[patent_app_country] => US
[patent_app_date] => 2004-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 8702
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/084/07084685.pdf
[firstpage_image] =>[orig_patent_app_number] => 10711254
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711254 | Method and related apparatus for outputting clock through a data path | Sep 3, 2004 | Issued |
Array
(
[id] => 739783
[patent_doc_number] => 07034597
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-04-25
[patent_title] => 'Dynamic phase alignment of a clock and data signal using an adjustable clock delay line'
[patent_app_type] => utility
[patent_app_number] => 10/933742
[patent_app_country] => US
[patent_app_date] => 2004-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4381
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/034/07034597.pdf
[firstpage_image] =>[orig_patent_app_number] => 10933742
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/933742 | Dynamic phase alignment of a clock and data signal using an adjustable clock delay line | Sep 2, 2004 | Issued |
Array
(
[id] => 7031571
[patent_doc_number] => 20050030080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Method and circuitry for reducing duty cycle distortion in differential delay lines'
[patent_app_type] => utility
[patent_app_number] => 10/932668
[patent_app_country] => US
[patent_app_date] => 2004-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2723
[patent_no_of_claims] => 58
[patent_no_of_ind_claims] => 25
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20050030080.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932668
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932668 | Method and circuitry for reducing duty cycle distortion in differential delay lines | Aug 31, 2004 | Issued |