Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7196214 [patent_doc_number] => 20050041486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Delay locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/931843 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4096 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041486.pdf [firstpage_image] =>[orig_patent_app_number] => 10931843 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931843
Delay locked loop circuit with time delay quantifier and control Aug 30, 2004 Issued
Array ( [id] => 743621 [patent_doc_number] => 07030675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Apparatus and method for controlling a delay chain' [patent_app_type] => utility [patent_app_number] => 10/932642 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030675.pdf [firstpage_image] =>[orig_patent_app_number] => 10932642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932642
Apparatus and method for controlling a delay chain Aug 30, 2004 Issued
Array ( [id] => 5899023 [patent_doc_number] => 20060044026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method and apparatus for timing domain crossing' [patent_app_type] => utility [patent_app_number] => 10/931397 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6921 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044026.pdf [firstpage_image] =>[orig_patent_app_number] => 10931397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931397
Method and apparatus for timing domain crossing Aug 30, 2004 Issued
Array ( [id] => 681529 [patent_doc_number] => 07084688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Clock distribution providing optimal delay' [patent_app_type] => utility [patent_app_number] => 10/929630 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2255 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084688.pdf [firstpage_image] =>[orig_patent_app_number] => 10929630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929630
Clock distribution providing optimal delay Aug 29, 2004 Issued
Array ( [id] => 664469 [patent_doc_number] => 07102400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'Phase locked loop charge pump and method of operation' [patent_app_type] => utility [patent_app_number] => 10/929158 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4989 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102400.pdf [firstpage_image] =>[orig_patent_app_number] => 10929158 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929158
Phase locked loop charge pump and method of operation Aug 29, 2004 Issued
Array ( [id] => 5899018 [patent_doc_number] => 20060044021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'FALSE-LOCK-FREE DELAY LOCKED LOOP CIRCUIT AND METHOD' [patent_app_type] => utility [patent_app_number] => 10/929180 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8811 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044021.pdf [firstpage_image] =>[orig_patent_app_number] => 10929180 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929180
False-lock-free delay locked loop circuit and method Aug 29, 2004 Issued
Array ( [id] => 688127 [patent_doc_number] => 07078951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal' [patent_app_type] => utility [patent_app_number] => 10/928424 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 6408 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078951.pdf [firstpage_image] =>[orig_patent_app_number] => 10928424 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928424
System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Aug 26, 2004 Issued
Array ( [id] => 730882 [patent_doc_number] => 07042265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Interlaced delay-locked loops for controlling memory-circuit timing' [patent_app_type] => utility [patent_app_number] => 10/914757 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4716 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042265.pdf [firstpage_image] =>[orig_patent_app_number] => 10914757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914757
Interlaced delay-locked loops for controlling memory-circuit timing Aug 8, 2004 Issued
Array ( [id] => 646732 [patent_doc_number] => 07119582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Phase detection in a sync pulse generator' [patent_app_type] => utility [patent_app_number] => 10/898693 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 9485 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119582.pdf [firstpage_image] =>[orig_patent_app_number] => 10898693 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898693
Phase detection in a sync pulse generator Jul 22, 2004 Issued
Array ( [id] => 775108 [patent_doc_number] => 07002382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Phase locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/895080 [patent_app_country] => US [patent_app_date] => 2004-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4677 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002382.pdf [firstpage_image] =>[orig_patent_app_number] => 10895080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895080
Phase locked loop circuit Jul 20, 2004 Issued
Array ( [id] => 5763555 [patent_doc_number] => 20060017479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'METHOD AND APPARATUS FOR DIGITAL PHASE GENERATION AT HIGH FREQUENCIES' [patent_app_type] => utility [patent_app_number] => 10/896159 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7798 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20060017479.pdf [firstpage_image] =>[orig_patent_app_number] => 10896159 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/896159
Method and apparatus for digital phase generation at high frequencies Jul 19, 2004 Issued
Array ( [id] => 688126 [patent_doc_number] => 07078950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Delay-locked loop with feedback compensation' [patent_app_type] => utility [patent_app_number] => 10/895649 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3891 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078950.pdf [firstpage_image] =>[orig_patent_app_number] => 10895649 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895649
Delay-locked loop with feedback compensation Jul 19, 2004 Issued
Array ( [id] => 726402 [patent_doc_number] => 07046069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method to reduce inductive effects of current variations by internal clock phase shifting' [patent_app_type] => utility [patent_app_number] => 10/894148 [patent_app_country] => US [patent_app_date] => 2004-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2508 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046069.pdf [firstpage_image] =>[orig_patent_app_number] => 10894148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/894148
Method to reduce inductive effects of current variations by internal clock phase shifting Jul 18, 2004 Issued
Array ( [id] => 7200596 [patent_doc_number] => 20050052252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Synchronizing unit for redundant system clocks' [patent_app_type] => utility [patent_app_number] => 10/891886 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7118 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052252.pdf [firstpage_image] =>[orig_patent_app_number] => 10891886 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891886
Synchronizing unit for redundant system clocks Jul 14, 2004 Abandoned
Array ( [id] => 656215 [patent_doc_number] => 07109767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'Generating different delay ratios for a strobe delay' [patent_app_type] => utility [patent_app_number] => 10/889610 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2990 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109767.pdf [firstpage_image] =>[orig_patent_app_number] => 10889610 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889610
Generating different delay ratios for a strobe delay Jul 11, 2004 Issued
Array ( [id] => 5736525 [patent_doc_number] => 20060006915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Signal slew rate control for image sensors' [patent_app_type] => utility [patent_app_number] => 10/887891 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4737 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20060006915.pdf [firstpage_image] =>[orig_patent_app_number] => 10887891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/887891
Signal slew rate control for image sensors Jul 11, 2004 Abandoned
Array ( [id] => 762628 [patent_doc_number] => 07012472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Digital control loop to improve phase noise performance and RX/TX linearity' [patent_app_type] => utility [patent_app_number] => 10/888861 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 5290 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012472.pdf [firstpage_image] =>[orig_patent_app_number] => 10888861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/888861
Digital control loop to improve phase noise performance and RX/TX linearity Jul 8, 2004 Issued
Array ( [id] => 756980 [patent_doc_number] => 07019569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Method of implementing multi-transfer curve phase lock loop' [patent_app_type] => utility [patent_app_number] => 10/888878 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2182 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019569.pdf [firstpage_image] =>[orig_patent_app_number] => 10888878 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/888878
Method of implementing multi-transfer curve phase lock loop Jul 8, 2004 Issued
Array ( [id] => 5893959 [patent_doc_number] => 20060002497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'PHASE ADJUSTMENT METHOD AND CIRCUIT FOR DLL-BASED SERIAL DATA LINK TRANSCEIVERS' [patent_app_type] => utility [patent_app_number] => 10/882428 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2949 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20060002497.pdf [firstpage_image] =>[orig_patent_app_number] => 10882428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/882428
Phase adjustment method and circuit for DLL-based serial data link transceivers Jul 1, 2004 Issued
Array ( [id] => 664467 [patent_doc_number] => 07102398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'Circuit for two PLLs for horizontal deflection' [patent_app_type] => utility [patent_app_number] => 10/880954 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8046 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102398.pdf [firstpage_image] =>[orig_patent_app_number] => 10880954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880954
Circuit for two PLLs for horizontal deflection Jun 29, 2004 Issued
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