Qian Yang

Array ( [id] => 7609303 [patent_doc_number] => 06998886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-14 [patent_title] => 'Apparatus and method for PLL with equalizing pulse removal' [patent_app_type] => utility [patent_app_number] => 10/881483 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998886.pdf [firstpage_image] =>[orig_patent_app_number] => 10881483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 703660 [patent_doc_number] => 07064617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method and apparatus for temperature compensation' [patent_app_type] => utility [patent_app_number] => 10/878196 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10491 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064617.pdf [firstpage_image] =>[orig_patent_app_number] => 10878196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 412179 [patent_doc_number] => 07282976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Apparatus and method for duty cycle correction' [patent_app_type] => utility [patent_app_number] => 10/876209 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2297 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282976.pdf [firstpage_image] =>[orig_patent_app_number] => 10876209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7149032 [patent_doc_number] => 20050024106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Charge pump system for fast locking phase lock loop' [patent_app_type] => utility [patent_app_number] => 10/874641 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5153 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024106.pdf [firstpage_image] =>[orig_patent_app_number] => 10874641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 630911 [patent_doc_number] => 07132872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Apparatus and method for generating a phase delay' [patent_app_type] => utility [patent_app_number] => 10/710175 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1885 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132872.pdf [firstpage_image] =>[orig_patent_app_number] => 10710175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1006394 [patent_doc_number] => 06906565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Fast lock phase lock loop and method thereof' [patent_app_type] => utility [patent_app_number] => 10/874646 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5645 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906565.pdf [firstpage_image] =>[orig_patent_app_number] => 10874646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7149041 [patent_doc_number] => 20050024112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Pulse width modulated common mode feedback loop and method for differential charge pump' [patent_app_type] => utility [patent_app_number] => 10/873318 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3898 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024112.pdf [firstpage_image] =>[orig_patent_app_number] => 10873318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 651433 [patent_doc_number] => 07113011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Low power PLL for PWM switching digital control power supply' [patent_app_type] => utility [patent_app_number] => 10/872702 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6809 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113011.pdf [firstpage_image] =>[orig_patent_app_number] => 10872702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 721773 [patent_doc_number] => 07049864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Apparatus and method for high frequency state machine divider with low power consumption' [patent_app_type] => utility [patent_app_number] => 10/710115 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5485 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049864.pdf [firstpage_image] =>[orig_patent_app_number] => 10710115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 726396 [patent_doc_number] => 07046066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method and/or apparatus for generating a write gated clock signal' [patent_app_type] => utility [patent_app_number] => 10/867899 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3135 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046066.pdf [firstpage_image] =>[orig_patent_app_number] => 10867899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7239208 [patent_doc_number] => 20050140402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Frequency converter' [patent_app_type] => utility [patent_app_number] => 10/866458 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3625 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140402.pdf [firstpage_image] =>[orig_patent_app_number] => 10866458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7023384 [patent_doc_number] => 20050017778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Pulse signal generator and display device' [patent_app_type] => utility [patent_app_number] => 10/863184 [patent_app_country] => US [patent_app_date] => 2004-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017778.pdf [firstpage_image] =>[orig_patent_app_number] => 10863184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 638845 [patent_doc_number] => 07126399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Memory interface phase-shift circuitry to support multiple frequency ranges' [patent_app_type] => utility [patent_app_number] => 10/857221 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 8648 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126399.pdf [firstpage_image] =>[orig_patent_app_number] => 10857221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6942964 [patent_doc_number] => 20050195012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/853260 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195012.pdf [firstpage_image] =>[orig_patent_app_number] => 10853260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 681526 [patent_doc_number] => 07084686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal' [patent_app_type] => utility [patent_app_number] => 10/854849 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 5824 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084686.pdf [firstpage_image] =>[orig_patent_app_number] => 10854849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7364574 [patent_doc_number] => 20040217781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Diode multiplexer circuit and electronic device incorporating the same' [patent_app_type] => new [patent_app_number] => 10/853350 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5475 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217781.pdf [firstpage_image] =>[orig_patent_app_number] => 10853350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7059303 [patent_doc_number] => 20050001662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'System with phase jumping locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/852650 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 26859 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001662.pdf [firstpage_image] =>[orig_patent_app_number] => 10852650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7292408 [patent_doc_number] => 20040212411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => new [patent_app_number] => 10/851891 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14397 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212411.pdf [firstpage_image] =>[orig_patent_app_number] => 10851891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 739760 [patent_doc_number] => 07034592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => utility [patent_app_number] => 10/851905 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 14294 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/034/07034592.pdf [firstpage_image] =>[orig_patent_app_number] => 10851905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1009916 [patent_doc_number] => 06900680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => utility [patent_app_number] => 10/851272 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 14312 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900680.pdf [firstpage_image] =>[orig_patent_app_number] => 10851272 [rel_patent_id] =>[rel_patent_doc_number] =>)