Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7364593 [patent_doc_number] => 20040217786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => new [patent_app_number] => 10/851271 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14397 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217786.pdf [firstpage_image] =>[orig_patent_app_number] => 10851271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851271
Clock controlling method and circuit May 20, 2004 Issued
Array ( [id] => 5713631 [patent_doc_number] => 20060076994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Pulse generator' [patent_app_type] => utility [patent_app_number] => 10/543534 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13415 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076994.pdf [firstpage_image] =>[orig_patent_app_number] => 10543534 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/543534
Pulse generator May 18, 2004 Issued
Array ( [id] => 7012610 [patent_doc_number] => 20050065745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Method and apparatus for numeric optimization of the control of a delay-locked loop in a network device' [patent_app_type] => utility [patent_app_number] => 10/845356 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4376 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20050065745.pdf [firstpage_image] =>[orig_patent_app_number] => 10845356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/845356
Method and apparatus for numeric optimization of the control of a delay-locked loop in a network device May 13, 2004 Issued
Array ( [id] => 7414410 [patent_doc_number] => 20040207436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Timing generating apparatus and test apparatus' [patent_app_type] => new [patent_app_number] => 10/844248 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6669 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20040207436.pdf [firstpage_image] =>[orig_patent_app_number] => 10844248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/844248
Timing generating apparatus and test apparatus May 11, 2004 Issued
Array ( [id] => 938775 [patent_doc_number] => 06972604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Circuit for compensating LPF capacitor charge leakage in phase locked loop systems' [patent_app_type] => utility [patent_app_number] => 10/840562 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972604.pdf [firstpage_image] =>[orig_patent_app_number] => 10840562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840562
Circuit for compensating LPF capacitor charge leakage in phase locked loop systems May 5, 2004 Issued
Array ( [id] => 7273548 [patent_doc_number] => 20040232999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Section selection loop filter and phase locked loop circuit having the same' [patent_app_type] => new [patent_app_number] => 10/840491 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5162 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232999.pdf [firstpage_image] =>[orig_patent_app_number] => 10840491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840491
Section selection loop filter and phase locked loop circuit having the same May 5, 2004 Issued
Array ( [id] => 770685 [patent_doc_number] => 07005904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Duty cycle correction' [patent_app_type] => utility [patent_app_number] => 10/836754 [patent_app_country] => US [patent_app_date] => 2004-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/005/07005904.pdf [firstpage_image] =>[orig_patent_app_number] => 10836754 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/836754
Duty cycle correction Apr 29, 2004 Issued
Array ( [id] => 7222550 [patent_doc_number] => 20050077937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Current starved DAC-controlled delay locked loop' [patent_app_type] => utility [patent_app_number] => 10/836704 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2400 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077937.pdf [firstpage_image] =>[orig_patent_app_number] => 10836704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/836704
Current starved DAC-controlled delay locked loop Apr 28, 2004 Issued
Array ( [id] => 474548 [patent_doc_number] => 07230495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Phase-locked loop circuits with reduced lock time' [patent_app_type] => utility [patent_app_number] => 10/834775 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4486 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230495.pdf [firstpage_image] =>[orig_patent_app_number] => 10834775 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834775
Phase-locked loop circuits with reduced lock time Apr 27, 2004 Issued
Array ( [id] => 7149008 [patent_doc_number] => 20050024094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Rotational frequency detector system' [patent_app_type] => utility [patent_app_number] => 10/830664 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6701 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024094.pdf [firstpage_image] =>[orig_patent_app_number] => 10830664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/830664
Rotational frequency detector system Apr 22, 2004 Issued
Array ( [id] => 793527 [patent_doc_number] => 06982573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Switchable clock source' [patent_app_type] => utility [patent_app_number] => 10/827675 [patent_app_country] => US [patent_app_date] => 2004-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4621 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982573.pdf [firstpage_image] =>[orig_patent_app_number] => 10827675 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/827675
Switchable clock source Apr 18, 2004 Issued
Array ( [id] => 509194 [patent_doc_number] => 07202714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Amplifier circuit with output delay selectively changed according to common mode voltage level, associated replica delay circuit and internal clock generator' [patent_app_type] => utility [patent_app_number] => 10/824361 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5778 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202714.pdf [firstpage_image] =>[orig_patent_app_number] => 10824361 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/824361
Amplifier circuit with output delay selectively changed according to common mode voltage level, associated replica delay circuit and internal clock generator Apr 14, 2004 Issued
Array ( [id] => 550792 [patent_doc_number] => 07170332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Reference signal generators' [patent_app_type] => utility [patent_app_number] => 10/825891 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7186 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170332.pdf [firstpage_image] =>[orig_patent_app_number] => 10825891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/825891
Reference signal generators Apr 14, 2004 Issued
Array ( [id] => 752653 [patent_doc_number] => 07023263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Low pass filter' [patent_app_type] => utility [patent_app_number] => 10/709101 [patent_app_country] => US [patent_app_date] => 2004-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2559 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023263.pdf [firstpage_image] =>[orig_patent_app_number] => 10709101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709101
Low pass filter Apr 13, 2004 Issued
Array ( [id] => 7273515 [patent_doc_number] => 20040232966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Multiple clocks with superperiod' [patent_app_type] => new [patent_app_number] => 10/814021 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7687 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232966.pdf [firstpage_image] =>[orig_patent_app_number] => 10814021 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814021
Multiple clocks with superperiod Mar 30, 2004 Issued
Array ( [id] => 7016937 [patent_doc_number] => 20050218955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Adaptive frequency clock generation system' [patent_app_type] => utility [patent_app_number] => 10/813551 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5001 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20050218955.pdf [firstpage_image] =>[orig_patent_app_number] => 10813551 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/813551
Adaptive frequency clock generation system Mar 30, 2004 Issued
Array ( [id] => 7016984 [patent_doc_number] => 20050219002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Tuning an oscillator' [patent_app_type] => utility [patent_app_number] => 10/814406 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3876 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20050219002.pdf [firstpage_image] =>[orig_patent_app_number] => 10814406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814406
Tuning an oscillator Mar 30, 2004 Abandoned
Array ( [id] => 946926 [patent_doc_number] => 06965260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'System and method for increasing effective pulse-width modulated drive signal resolution and converter controller incorporating the same' [patent_app_type] => utility [patent_app_number] => 10/812531 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3871 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965260.pdf [firstpage_image] =>[orig_patent_app_number] => 10812531 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/812531
System and method for increasing effective pulse-width modulated drive signal resolution and converter controller incorporating the same Mar 29, 2004 Issued
Array ( [id] => 651432 [patent_doc_number] => 07113010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Clock distortion detector using a synchronous mirror delay circuit' [patent_app_type] => utility [patent_app_number] => 10/809826 [patent_app_country] => US [patent_app_date] => 2004-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4391 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113010.pdf [firstpage_image] =>[orig_patent_app_number] => 10809826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/809826
Clock distortion detector using a synchronous mirror delay circuit Mar 25, 2004 Issued
Array ( [id] => 5202844 [patent_doc_number] => 20070024323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Wide-band circuit' [patent_app_type] => utility [patent_app_number] => 10/551413 [patent_app_country] => US [patent_app_date] => 2004-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 15992 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20070024323.pdf [firstpage_image] =>[orig_patent_app_number] => 10551413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/551413
Wide-band circuit coupled through a transmission line Mar 23, 2004 Issued
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