Qian Yang
Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )
Most Active Art Unit | 2668 |
Art Unit(s) | 2625, 2674, 2668, 2662 |
Total Applications | 1035 |
Issued Applications | 734 |
Pending Applications | 61 |
Abandoned Applications | 239 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 793540
[patent_doc_number] => 06982586
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-03
[patent_title] => 'Systems and methods for clock generation using hot-swappable oscillators'
[patent_app_type] => utility
[patent_app_number] => 10/805863
[patent_app_country] => US
[patent_app_date] => 2004-03-22
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[pdf_file] => patents/06/982/06982586.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/805863 | Systems and methods for clock generation using hot-swappable oscillators | Mar 21, 2004 | Issued |
Array
(
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[patent_doc_number] => 07019576
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[patent_kind] => B1
[patent_issue_date] => 2006-03-28
[patent_title] => 'Delay circuit that scales with clock cycle time'
[patent_app_type] => utility
[patent_app_number] => 10/804988
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[patent_app_date] => 2004-03-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/804988 | Delay circuit that scales with clock cycle time | Mar 17, 2004 | Issued |
Array
(
[id] => 7424654
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[patent_issue_date] => 2004-09-23
[patent_title] => 'Analog signal level detecting apparatus'
[patent_app_type] => new
[patent_app_number] => 10/799668
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/799668 | Analog signal level detecting apparatus | Mar 14, 2004 | Issued |
Array
(
[id] => 7273509
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[patent_issue_date] => 2004-11-25
[patent_title] => 'Phase-error-compensation techniques in a fractional-N PLL frequency synthesizer'
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Array
(
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[patent_title] => 'Delay circuit with more-responsively adapting delay time'
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Array
(
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[patent_title] => 'Low noise level shifting circuits and methods and systems using the same'
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Array
(
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[patent_title] => 'Phase-locked loop circuit with switched-capacitor conditioning of the control current'
[patent_app_type] => utility
[patent_app_number] => 10/798244
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/798244 | Phase-locked loop circuit with switched-capacitor conditioning of the control current | Mar 10, 2004 | Issued |
Array
(
[id] => 7607009
[patent_doc_number] => 07098707
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[patent_kind] => B2
[patent_issue_date] => 2006-08-29
[patent_title] => 'Highly configurable PLL architecture for programmable logic'
[patent_app_type] => utility
[patent_app_number] => 10/797836
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/797836 | Highly configurable PLL architecture for programmable logic | Mar 8, 2004 | Issued |
Array
(
[id] => 7177835
[patent_doc_number] => 20050189974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'A MULTI-STAGE DELAY CLOCK GENERATOR'
[patent_app_type] => utility
[patent_app_number] => 10/708373
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708373 | Multi-stage delay clock generator | Feb 25, 2004 | Issued |
Array
(
[id] => 7144673
[patent_doc_number] => 20040169538
[patent_country] => US
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[patent_issue_date] => 2004-09-02
[patent_title] => 'DLL circuit'
[patent_app_type] => new
[patent_app_number] => 10/785015
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785015 | DLL circuit | Feb 24, 2004 | Issued |
Array
(
[id] => 7125549
[patent_doc_number] => 20050057293
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[patent_issue_date] => 2005-03-17
[patent_title] => 'Stable timing clock circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/781877 | Stable timing clock circuit | Feb 19, 2004 | Issued |
Array
(
[id] => 7417505
[patent_doc_number] => 20040160281
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[patent_issue_date] => 2004-08-19
[patent_title] => 'Circuitry to reduce PLL lock acquisition time'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/780493 | Circuitry to reduce PLL lock acquisition time | Feb 16, 2004 | Issued |
Array
(
[id] => 783728
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[patent_title] => 'Pulse duty cycle automatic correction device and method thereof'
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Array
(
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[patent_title] => 'Clock generating circuit with a frequency multiplying circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778120 | Clock generating circuit with a frequency multiplying circuit | Feb 16, 2004 | Issued |
Array
(
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[patent_title] => 'Phase locked loop circuit'
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Array
(
[id] => 7292407
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/776931 | Reduced-size integrated phase-locked loop | Feb 10, 2004 | Issued |
Array
(
[id] => 485051
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[patent_title] => 'Pulse-width modulator circuit and method for controlling a pulse width modulator circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/532821 | Pulse-width modulator circuit and method for controlling a pulse width modulator circuit | Jan 7, 2004 | Issued |
Array
(
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Array
(
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Array
(
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[patent_title] => 'Level shifter circuit'
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[firstpage_image] =>[orig_patent_app_number] => 10747240
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/747240 | Level shifter circuit | Dec 29, 2003 | Abandoned |