Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 793540 [patent_doc_number] => 06982586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Systems and methods for clock generation using hot-swappable oscillators' [patent_app_type] => utility [patent_app_number] => 10/805863 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982586.pdf [firstpage_image] =>[orig_patent_app_number] => 10805863 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805863
Systems and methods for clock generation using hot-swappable oscillators Mar 21, 2004 Issued
Array ( [id] => 757017 [patent_doc_number] => 07019576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Delay circuit that scales with clock cycle time' [patent_app_type] => utility [patent_app_number] => 10/804988 [patent_app_country] => US [patent_app_date] => 2004-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019576.pdf [firstpage_image] =>[orig_patent_app_number] => 10804988 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/804988
Delay circuit that scales with clock cycle time Mar 17, 2004 Issued
Array ( [id] => 7424654 [patent_doc_number] => 20040183709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Analog signal level detecting apparatus' [patent_app_type] => new [patent_app_number] => 10/799668 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4090 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183709.pdf [firstpage_image] =>[orig_patent_app_number] => 10799668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/799668
Analog signal level detecting apparatus Mar 14, 2004 Issued
Array ( [id] => 7273509 [patent_doc_number] => 20040232960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Phase-error-compensation techniques in a fractional-N PLL frequency synthesizer' [patent_app_type] => new [patent_app_number] => 10/801502 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6904 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232960.pdf [firstpage_image] =>[orig_patent_app_number] => 10801502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801502
Phase-error-compensation techniques in a fractional-N PLL frequency synthesizer Mar 14, 2004 Issued
Array ( [id] => 7059308 [patent_doc_number] => 20050001667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Delay circuit with more-responsively adapting delay time' [patent_app_type] => utility [patent_app_number] => 10/798560 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3633 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001667.pdf [firstpage_image] =>[orig_patent_app_number] => 10798560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798560
Delay circuit with more-responsively adapting delay time Mar 11, 2004 Issued
Array ( [id] => 7616553 [patent_doc_number] => 06946890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Low noise level shifting circuits and methods and systems using the same' [patent_app_type] => utility [patent_app_number] => 10/798661 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/946/06946890.pdf [firstpage_image] =>[orig_patent_app_number] => 10798661 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798661
Low noise level shifting circuits and methods and systems using the same Mar 10, 2004 Issued
Array ( [id] => 7059330 [patent_doc_number] => 20050001689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Phase-locked loop circuit with switched-capacitor conditioning of the control current' [patent_app_type] => utility [patent_app_number] => 10/798244 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6271 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001689.pdf [firstpage_image] =>[orig_patent_app_number] => 10798244 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798244
Phase-locked loop circuit with switched-capacitor conditioning of the control current Mar 10, 2004 Issued
Array ( [id] => 7607009 [patent_doc_number] => 07098707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Highly configurable PLL architecture for programmable logic' [patent_app_type] => utility [patent_app_number] => 10/797836 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6157 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098707.pdf [firstpage_image] =>[orig_patent_app_number] => 10797836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/797836
Highly configurable PLL architecture for programmable logic Mar 8, 2004 Issued
Array ( [id] => 7177835 [patent_doc_number] => 20050189974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'A MULTI-STAGE DELAY CLOCK GENERATOR' [patent_app_type] => utility [patent_app_number] => 10/708373 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3403 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20050189974.pdf [firstpage_image] =>[orig_patent_app_number] => 10708373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708373
Multi-stage delay clock generator Feb 25, 2004 Issued
Array ( [id] => 7144673 [patent_doc_number] => 20040169538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'DLL circuit' [patent_app_type] => new [patent_app_number] => 10/785015 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8479 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20040169538.pdf [firstpage_image] =>[orig_patent_app_number] => 10785015 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785015
DLL circuit Feb 24, 2004 Issued
Array ( [id] => 7125549 [patent_doc_number] => 20050057293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Stable timing clock circuit' [patent_app_type] => utility [patent_app_number] => 10/781877 [patent_app_country] => US [patent_app_date] => 2004-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2174 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057293.pdf [firstpage_image] =>[orig_patent_app_number] => 10781877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781877
Stable timing clock circuit Feb 19, 2004 Issued
Array ( [id] => 7417505 [patent_doc_number] => 20040160281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Circuitry to reduce PLL lock acquisition time' [patent_app_type] => new [patent_app_number] => 10/780493 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3061 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160281.pdf [firstpage_image] =>[orig_patent_app_number] => 10780493 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/780493
Circuitry to reduce PLL lock acquisition time Feb 16, 2004 Issued
Array ( [id] => 783728 [patent_doc_number] => 06992516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Pulse duty cycle automatic correction device and method thereof' [patent_app_type] => utility [patent_app_number] => 10/778402 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2943 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992516.pdf [firstpage_image] =>[orig_patent_app_number] => 10778402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778402
Pulse duty cycle automatic correction device and method thereof Feb 16, 2004 Issued
Array ( [id] => 938779 [patent_doc_number] => 06972608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Clock generating circuit with a frequency multiplying circuit' [patent_app_type] => utility [patent_app_number] => 10/778120 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5671 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972608.pdf [firstpage_image] =>[orig_patent_app_number] => 10778120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778120
Clock generating circuit with a frequency multiplying circuit Feb 16, 2004 Issued
Array ( [id] => 976446 [patent_doc_number] => 06933790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Phase locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/777481 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 9132 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933790.pdf [firstpage_image] =>[orig_patent_app_number] => 10777481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777481
Phase locked loop circuit Feb 11, 2004 Issued
Array ( [id] => 7292407 [patent_doc_number] => 20040212410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Reduced-size integrated phase-locked loop' [patent_app_type] => new [patent_app_number] => 10/776931 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2635 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212410.pdf [firstpage_image] =>[orig_patent_app_number] => 10776931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776931
Reduced-size integrated phase-locked loop Feb 10, 2004 Issued
Array ( [id] => 485051 [patent_doc_number] => 07221203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Pulse-width modulator circuit and method for controlling a pulse width modulator circuit' [patent_app_type] => utility [patent_app_number] => 10/532821 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2340 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221203.pdf [firstpage_image] =>[orig_patent_app_number] => 10532821 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/532821
Pulse-width modulator circuit and method for controlling a pulse width modulator circuit Jan 7, 2004 Issued
Array ( [id] => 7239271 [patent_doc_number] => 20050140415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Timing circuit for separate positive and negative edge placement in a switching DC-DC converter' [patent_app_type] => utility [patent_app_number] => 10/748298 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4384 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140415.pdf [firstpage_image] =>[orig_patent_app_number] => 10748298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748298
Timing circuit for separate positive and negative edge placement in a switching DC-DC converter Dec 30, 2003 Issued
Array ( [id] => 7239262 [patent_doc_number] => 20050140412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Interpolation delay cell for 2ps resolution jitter injector in optical link transceiver' [patent_app_type] => utility [patent_app_number] => 10/748300 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4745 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140412.pdf [firstpage_image] =>[orig_patent_app_number] => 10748300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748300
Interpolation delay cell for 2ps resolution jitter injector in optical link transceiver Dec 30, 2003 Issued
Array ( [id] => 7200371 [patent_doc_number] => 20050052214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Level shifter circuit' [patent_app_type] => utility [patent_app_number] => 10/747240 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8546 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052214.pdf [firstpage_image] =>[orig_patent_app_number] => 10747240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747240
Level shifter circuit Dec 29, 2003 Abandoned
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