Qian Yang
Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )
Most Active Art Unit | 2668 |
Art Unit(s) | 2625, 2674, 2668, 2662 |
Total Applications | 1035 |
Issued Applications | 734 |
Pending Applications | 61 |
Abandoned Applications | 239 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7239273
[patent_doc_number] => 20050140416
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[patent_title] => 'Programmable direct interpolating delay locked loop'
[patent_app_type] => utility
[patent_app_number] => 10/746105
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746105 | Programmable direct interpolating delay locked loop | Dec 23, 2003 | Issued |
Array
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[patent_title] => 'Circuit for generating phase comparison signal'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746519 | Circuit for generating phase comparison signal | Dec 23, 2003 | Issued |
Array
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[patent_title] => 'Low power circuit with proper slew rate by automatic adjustment of bias current'
[patent_app_type] => reissue
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Array
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[patent_title] => 'Centralizing the lock point of a synchronous circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/730609 | Centralizing the lock point of a synchronous circuit | Dec 7, 2003 | Issued |
Array
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Array
(
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[patent_title] => 'Clock signal regeneration circuitry'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728262 | Clock signal regeneration circuitry | Dec 3, 2003 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/725847 | Programmable jitter signal generator | Dec 1, 2003 | Issued |
Array
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[patent_title] => 'Circuit and method for inducing jitter to a signal'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726079 | Circuit and method for inducing jitter to a signal | Nov 30, 2003 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/714844 | Single-ended differential circuit using complementary devices | Nov 17, 2003 | Issued |
Array
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[patent_title] => 'Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/696920 | DELAY LOCKED LOOP PHASE BLENDER CIRCUIT | Oct 29, 2003 | Abandoned |
Array
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Array
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Array
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