Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7239273 [patent_doc_number] => 20050140416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Programmable direct interpolating delay locked loop' [patent_app_type] => utility [patent_app_number] => 10/746105 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3760 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140416.pdf [firstpage_image] =>[orig_patent_app_number] => 10746105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746105
Programmable direct interpolating delay locked loop Dec 23, 2003 Issued
Array ( [id] => 712707 [patent_doc_number] => 07057428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Circuit for generating phase comparison signal' [patent_app_type] => utility [patent_app_number] => 10/746519 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2385 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057428.pdf [firstpage_image] =>[orig_patent_app_number] => 10746519 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746519
Circuit for generating phase comparison signal Dec 23, 2003 Issued
Array ( [id] => 883949 [patent_doc_number] => RE040168 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2008-03-25 [patent_title] => 'Low power circuit with proper slew rate by automatic adjustment of bias current' [patent_app_type] => reissue [patent_app_number] => 10/740901 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040168.pdf [firstpage_image] =>[orig_patent_app_number] => 10740901 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/740901
Low power circuit with proper slew rate by automatic adjustment of bias current Dec 21, 2003 Issued
Array ( [id] => 7607002 [patent_doc_number] => 07098714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Centralizing the lock point of a synchronous circuit' [patent_app_type] => utility [patent_app_number] => 10/730609 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9850 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098714.pdf [firstpage_image] =>[orig_patent_app_number] => 10730609 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/730609
Centralizing the lock point of a synchronous circuit Dec 7, 2003 Issued
Array ( [id] => 7614833 [patent_doc_number] => 06897695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Semiconductor integrated circuit device and method of detecting delay error in the same' [patent_app_type] => utility [patent_app_number] => 10/729457 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7195 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897695.pdf [firstpage_image] =>[orig_patent_app_number] => 10729457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729457
Semiconductor integrated circuit device and method of detecting delay error in the same Dec 4, 2003 Issued
Array ( [id] => 938778 [patent_doc_number] => 06972607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Clock signal regeneration circuitry' [patent_app_type] => utility [patent_app_number] => 10/728262 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2959 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972607.pdf [firstpage_image] =>[orig_patent_app_number] => 10728262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728262
Clock signal regeneration circuitry Dec 3, 2003 Issued
Array ( [id] => 669252 [patent_doc_number] => 07095264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Programmable jitter signal generator' [patent_app_type] => utility [patent_app_number] => 10/725847 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2472 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/095/07095264.pdf [firstpage_image] =>[orig_patent_app_number] => 10725847 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725847
Programmable jitter signal generator Dec 1, 2003 Issued
Array ( [id] => 7319417 [patent_doc_number] => 20040135606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Circuit and method for inducing jitter to a signal' [patent_app_type] => new [patent_app_number] => 10/726079 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5848 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135606.pdf [firstpage_image] =>[orig_patent_app_number] => 10726079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726079
Circuit and method for inducing jitter to a signal Nov 30, 2003 Issued
Array ( [id] => 7461675 [patent_doc_number] => 20040095163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Single-ended differential circuit using complementary devices' [patent_app_type] => new [patent_app_number] => 10/714844 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6994 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095163.pdf [firstpage_image] =>[orig_patent_app_number] => 10714844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714844
Single-ended differential circuit using complementary devices Nov 17, 2003 Issued
Array ( [id] => 432813 [patent_doc_number] => 07265590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit' [patent_app_type] => utility [patent_app_number] => 10/713365 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7322 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265590.pdf [firstpage_image] =>[orig_patent_app_number] => 10713365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713365
Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit Nov 13, 2003 Issued
Array ( [id] => 7454942 [patent_doc_number] => 20040100331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Apparatus for controlling the frequency of received signals to a predetermined frequency' [patent_app_type] => new [patent_app_number] => 10/712055 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4683 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20040100331.pdf [firstpage_image] =>[orig_patent_app_number] => 10712055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712055
Apparatus for controlling the frequency of received signals to a predetermined frequency Nov 13, 2003 Issued
Array ( [id] => 7101941 [patent_doc_number] => 20050104667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Frequency synthesizer having PLL with an analog phase detector' [patent_app_type] => utility [patent_app_number] => 10/713717 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3258 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104667.pdf [firstpage_image] =>[orig_patent_app_number] => 10713717 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713717
Frequency synthesizer having PLL with an analog phase detector Nov 13, 2003 Issued
Array ( [id] => 6916033 [patent_doc_number] => 20050093594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'DELAY LOCKED LOOP PHASE BLENDER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 10/696920 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4549 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093594.pdf [firstpage_image] =>[orig_patent_app_number] => 10696920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696920
DELAY LOCKED LOOP PHASE BLENDER CIRCUIT Oct 29, 2003 Abandoned
Array ( [id] => 979517 [patent_doc_number] => 06930523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Apparatus and method for reflection delay splitting digital clock distribution' [patent_app_type] => utility [patent_app_number] => 10/697131 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3261 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930523.pdf [firstpage_image] =>[orig_patent_app_number] => 10697131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697131
Apparatus and method for reflection delay splitting digital clock distribution Oct 29, 2003 Issued
Array ( [id] => 6916030 [patent_doc_number] => 20050093591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Semidigital delay-locked loop using an analog-based finite state machine' [patent_app_type] => utility [patent_app_number] => 10/696139 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4493 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093591.pdf [firstpage_image] =>[orig_patent_app_number] => 10696139 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696139
Semidigital delay-locked loop using an analog-based finite state machine Oct 28, 2003 Issued
Array ( [id] => 7155567 [patent_doc_number] => 20050083089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Programmable phase-locked loop circuitry for programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/691152 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4190 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083089.pdf [firstpage_image] =>[orig_patent_app_number] => 10691152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/691152
Programmable phase-locked loop circuitry for programmable logic device Oct 20, 2003 Issued
Array ( [id] => 1054135 [patent_doc_number] => 06859073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Fast VCO calibration for frequency synthesizers' [patent_app_type] => utility [patent_app_number] => 10/687492 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 1703 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859073.pdf [firstpage_image] =>[orig_patent_app_number] => 10687492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687492
Fast VCO calibration for frequency synthesizers Oct 16, 2003 Issued
Array ( [id] => 1083827 [patent_doc_number] => 06833744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Circuit for correcting duty factor of clock signal' [patent_app_type] => B2 [patent_app_number] => 10/688685 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833744.pdf [firstpage_image] =>[orig_patent_app_number] => 10688685 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688685
Circuit for correcting duty factor of clock signal Oct 16, 2003 Issued
Array ( [id] => 7296625 [patent_doc_number] => 20040124931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Circular geometry oscillators' [patent_app_type] => new [patent_app_number] => 10/687679 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3070 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124931.pdf [firstpage_image] =>[orig_patent_app_number] => 10687679 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687679
Circular geometry oscillators Oct 16, 2003 Issued
Array ( [id] => 500721 [patent_doc_number] => 07208988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Clock generator' [patent_app_type] => utility [patent_app_number] => 10/684704 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6823 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208988.pdf [firstpage_image] =>[orig_patent_app_number] => 10684704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684704
Clock generator Oct 14, 2003 Issued
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