Qian Yang
Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )
Most Active Art Unit | 2668 |
Art Unit(s) | 2625, 2674, 2668, 2662 |
Total Applications | 1035 |
Issued Applications | 734 |
Pending Applications | 61 |
Abandoned Applications | 239 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 726394
[patent_doc_number] => 07046065
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[patent_kind] => B2
[patent_issue_date] => 2006-05-16
[patent_title] => 'Decimal set point clock generator and application of this clock generator to UART circuit'
[patent_app_type] => utility
[patent_app_number] => 10/684823
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/684823 | Decimal set point clock generator and application of this clock generator to UART circuit | Oct 13, 2003 | Issued |
Array
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[patent_doc_number] => 20040232967
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[patent_kind] => A1
[patent_issue_date] => 2004-11-25
[patent_title] => 'Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit'
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Array
(
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[patent_doc_number] => 06982576
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[patent_issue_date] => 2006-01-03
[patent_title] => 'Signal delay compensating circuit'
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Array
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[patent_issue_date] => 2005-05-10
[patent_title] => 'Current pulse receiving circuit'
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Array
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Array
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Array
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Array
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[patent_title] => 'DLL Circuit'
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Array
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[patent_title] => 'Phase locked loop circuit with an unlock detection circuit and a switch'
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Array
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Array
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[id] => 997038
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[patent_title] => 'Frequency output generation through alternating between selected frequencies'
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Array
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[id] => 1086862
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[patent_title] => 'Reconfigurable filter architecture'
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Array
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Array
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Array
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Array
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