Search

Qian Yang

Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )

Most Active Art Unit
2668
Art Unit(s)
2625, 2674, 2668, 2662
Total Applications
1035
Issued Applications
734
Pending Applications
61
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 726394 [patent_doc_number] => 07046065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Decimal set point clock generator and application of this clock generator to UART circuit' [patent_app_type] => utility [patent_app_number] => 10/684823 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 7150 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046065.pdf [firstpage_image] =>[orig_patent_app_number] => 10684823 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684823
Decimal set point clock generator and application of this clock generator to UART circuit Oct 13, 2003 Issued
Array ( [id] => 7273516 [patent_doc_number] => 20040232967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit' [patent_app_type] => new [patent_app_number] => 10/682166 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12623 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232967.pdf [firstpage_image] =>[orig_patent_app_number] => 10682166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682166
Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit Oct 9, 2003 Issued
Array ( [id] => 793530 [patent_doc_number] => 06982576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Signal delay compensating circuit' [patent_app_type] => utility [patent_app_number] => 10/684187 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3842 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982576.pdf [firstpage_image] =>[orig_patent_app_number] => 10684187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684187
Signal delay compensating circuit Oct 9, 2003 Issued
Array ( [id] => 1019037 [patent_doc_number] => 06891408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Current pulse receiving circuit' [patent_app_type] => utility [patent_app_number] => 10/681306 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 15454 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891408.pdf [firstpage_image] =>[orig_patent_app_number] => 10681306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681306
Current pulse receiving circuit Oct 8, 2003 Issued
Array ( [id] => 7612255 [patent_doc_number] => 06903582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Integrated circuit timing debug apparatus and method' [patent_app_type] => utility [patent_app_number] => 10/682351 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12091 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903582.pdf [firstpage_image] =>[orig_patent_app_number] => 10682351 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682351
Integrated circuit timing debug apparatus and method Oct 8, 2003 Issued
Array ( [id] => 7436334 [patent_doc_number] => 20040066216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Differential output structure with reduced skew for a single input' [patent_app_type] => new [patent_app_number] => 10/678937 [patent_app_country] => US [patent_app_date] => 2003-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066216.pdf [firstpage_image] =>[orig_patent_app_number] => 10678937 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/678937
Differential output structure with reduced skew for a single input Oct 2, 2003 Issued
Array ( [id] => 1057234 [patent_doc_number] => 06856174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Versatile system for high resolution device calibration' [patent_app_type] => utility [patent_app_number] => 10/677105 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4357 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856174.pdf [firstpage_image] =>[orig_patent_app_number] => 10677105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677105
Versatile system for high resolution device calibration Sep 30, 2003 Issued
Array ( [id] => 7292410 [patent_doc_number] => 20040212413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'DLL Circuit' [patent_app_type] => new [patent_app_number] => 10/672990 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5060 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212413.pdf [firstpage_image] =>[orig_patent_app_number] => 10672990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/672990
DLL circuit Sep 25, 2003 Issued
Array ( [id] => 969045 [patent_doc_number] => 06940323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Phase locked loop circuit with an unlock detection circuit and a switch' [patent_app_type] => utility [patent_app_number] => 10/670516 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 8318 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940323.pdf [firstpage_image] =>[orig_patent_app_number] => 10670516 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/670516
Phase locked loop circuit with an unlock detection circuit and a switch Sep 25, 2003 Issued
Array ( [id] => 7619591 [patent_doc_number] => 06943595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Synchronization circuit' [patent_app_type] => utility [patent_app_number] => 10/670510 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8693 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943595.pdf [firstpage_image] =>[orig_patent_app_number] => 10670510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/670510
Synchronization circuit Sep 25, 2003 Issued
Array ( [id] => 997038 [patent_doc_number] => 06914463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Frequency output generation through alternating between selected frequencies' [patent_app_type] => utility [patent_app_number] => 10/671431 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5930 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914463.pdf [firstpage_image] =>[orig_patent_app_number] => 10671431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/671431
Frequency output generation through alternating between selected frequencies Sep 25, 2003 Issued
Array ( [id] => 1086862 [patent_doc_number] => 06831506 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Reconfigurable filter architecture' [patent_app_type] => B1 [patent_app_number] => 10/665234 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2555 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831506.pdf [firstpage_image] =>[orig_patent_app_number] => 10665234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/665234
Reconfigurable filter architecture Sep 16, 2003 Issued
Array ( [id] => 1044488 [patent_doc_number] => 06867627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics' [patent_app_type] => utility [patent_app_number] => 10/663624 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867627.pdf [firstpage_image] =>[orig_patent_app_number] => 10663624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/663624
Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics Sep 15, 2003 Issued
Array ( [id] => 7355555 [patent_doc_number] => 20040090255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Delay circuit with delay relatively independent of process, voltage, and temperature variations' [patent_app_type] => new [patent_app_number] => 10/661563 [patent_app_country] => US [patent_app_date] => 2003-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4607 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090255.pdf [firstpage_image] =>[orig_patent_app_number] => 10661563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/661563
Delay circuit and method with delay relatively independent of process, voltage, and temperature variations Sep 14, 2003 Issued
Array ( [id] => 1064088 [patent_doc_number] => 06850101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Single-line synchronizable oscillator circuit' [patent_app_type] => utility [patent_app_number] => 10/657506 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/850/06850101.pdf [firstpage_image] =>[orig_patent_app_number] => 10657506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657506
Single-line synchronizable oscillator circuit Sep 7, 2003 Issued
Array ( [id] => 7059307 [patent_doc_number] => 20050001666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'DELAY CIRCUIT HAVING FUNCTION OF FILTER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 10/656254 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5241 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001666.pdf [firstpage_image] =>[orig_patent_app_number] => 10656254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/656254
Delay circuit having function of filter circuit Sep 7, 2003 Issued
Array ( [id] => 775109 [patent_doc_number] => 07002383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-21 [patent_title] => 'Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)' [patent_app_type] => utility [patent_app_number] => 10/654711 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2403 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002383.pdf [firstpage_image] =>[orig_patent_app_number] => 10654711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654711
Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL) Sep 3, 2003 Issued
Array ( [id] => 1094280 [patent_doc_number] => 06825703 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Delay locked loop and method of driving the same' [patent_app_type] => B1 [patent_app_number] => 10/654498 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2711 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825703.pdf [firstpage_image] =>[orig_patent_app_number] => 10654498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654498
Delay locked loop and method of driving the same Sep 2, 2003 Issued
Array ( [id] => 7081072 [patent_doc_number] => 20050046452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'All digital PLL trimming circuit' [patent_app_type] => utility [patent_app_number] => 10/653614 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5975 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20050046452.pdf [firstpage_image] =>[orig_patent_app_number] => 10653614 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653614
All digital PLL trimming circuit Sep 1, 2003 Issued
Array ( [id] => 620684 [patent_doc_number] => 07142042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Nulled error amplifier' [patent_app_type] => utility [patent_app_number] => 10/651849 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3895 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/142/07142042.pdf [firstpage_image] =>[orig_patent_app_number] => 10651849 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651849
Nulled error amplifier Aug 28, 2003 Issued
Menu