Qian Yang
Examiner (ID: 3676, Phone: (571)270-7239 , Office: P/2674 )
Most Active Art Unit | 2668 |
Art Unit(s) | 2625, 2674, 2668, 2662 |
Total Applications | 1035 |
Issued Applications | 734 |
Pending Applications | 61 |
Abandoned Applications | 239 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7382140
[patent_doc_number] => 20040036515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-26
[patent_title] => 'Method and circuit for adjusting the timing of output data based on an operational mode of output drivers'
[patent_app_type] => new
[patent_app_number] => 10/651602
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20040036515.pdf
[firstpage_image] =>[orig_patent_app_number] => 10651602
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/651602 | Method and circuit for adjusting the timing of output data based on an operational mode of output drivers | Aug 28, 2003 | Issued |
Array
(
[id] => 1041379
[patent_doc_number] => 06870404
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Programmable differential capacitors for equalization circuits'
[patent_app_type] => utility
[patent_app_number] => 10/652863
[patent_app_country] => US
[patent_app_date] => 2003-08-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/652863 | Programmable differential capacitors for equalization circuits | Aug 27, 2003 | Issued |
Array
(
[id] => 1083820
[patent_doc_number] => 06833740
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-21
[patent_title] => 'Sinusoidal frequency generator and periodic signal converter using thereof'
[patent_app_type] => B2
[patent_app_number] => 10/649711
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/649711 | Sinusoidal frequency generator and periodic signal converter using thereof | Aug 25, 2003 | Issued |
Array
(
[id] => 7377234
[patent_doc_number] => 20040178834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Phase-locked loop integrated circuits that support clock signal updates during dead zone compensation time intervals'
[patent_app_type] => new
[patent_app_number] => 10/640075
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[patent_app_date] => 2003-08-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/640075 | Phase-locked loop integrated circuits that support clock signal updates during dead zone compensation time intervals | Aug 12, 2003 | Issued |
Array
(
[id] => 1022853
[patent_doc_number] => 06888385
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[patent_issue_date] => 2005-05-03
[patent_title] => 'Phase locked loop (PLL) for integrated circuits'
[patent_app_type] => utility
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639248 | Phase locked loop (PLL) for integrated circuits | Aug 11, 2003 | Issued |
Array
(
[id] => 7355533
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[patent_issue_date] => 2004-05-13
[patent_title] => 'Programmable timing generator with offset and width control using delay lock loop'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/637401 | Programmable timing generator with offset and width control using delay lock loop | Aug 7, 2003 | Abandoned |
Array
(
[id] => 991218
[patent_doc_number] => 06919745
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[patent_issue_date] => 2005-07-19
[patent_title] => 'Ring-resister controlled DLL with fine delay line and direct skew sensing detector'
[patent_app_type] => utility
[patent_app_number] => 10/635913
[patent_app_country] => US
[patent_app_date] => 2003-08-07
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[pdf_file] => patents/06/919/06919745.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635913 | Ring-resister controlled DLL with fine delay line and direct skew sensing detector | Aug 6, 2003 | Issued |
Array
(
[id] => 1098007
[patent_doc_number] => 06822486
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'Multiplexer methods and apparatus'
[patent_app_type] => B1
[patent_app_number] => 10/635968
[patent_app_country] => US
[patent_app_date] => 2003-08-07
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[pdf_file] => patents/06/822/06822486.pdf
[firstpage_image] =>[orig_patent_app_number] => 10635968
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635968 | Multiplexer methods and apparatus | Aug 6, 2003 | Issued |
Array
(
[id] => 7627692
[patent_doc_number] => 06806746
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-19
[patent_title] => 'Direct frequency synthesizer for offset loop synthesizer'
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[patent_app_number] => 10/633225
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[patent_app_date] => 2003-07-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/633225 | Direct frequency synthesizer for offset loop synthesizer | Jul 30, 2003 | Issued |
Array
(
[id] => 7149048
[patent_doc_number] => 20050024116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Delay matching for clock distribution in a logic circuit'
[patent_app_type] => utility
[patent_app_number] => 10/632651
[patent_app_country] => US
[patent_app_date] => 2003-07-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/632651 | Delay matching for clock distribution in a logic circuit | Jul 30, 2003 | Issued |
Array
(
[id] => 7629205
[patent_doc_number] => 06819152
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-16
[patent_title] => 'Circuitry for reducing leakage currents in a pre-charge circuit using very small MOSFET devices'
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[patent_app_number] => 10/630311
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[pdf_file] => patents/06/819/06819152.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/630311 | Circuitry for reducing leakage currents in a pre-charge circuit using very small MOSFET devices | Jul 29, 2003 | Issued |
Array
(
[id] => 1109615
[patent_doc_number] => 06809566
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[patent_issue_date] => 2004-10-26
[patent_title] => 'Low power differential-to-single-ended converter with good duty cycle performance'
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[patent_app_number] => 10/630153
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/630153 | Low power differential-to-single-ended converter with good duty cycle performance | Jul 29, 2003 | Issued |
Array
(
[id] => 712703
[patent_doc_number] => 07057426
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[patent_issue_date] => 2006-06-06
[patent_title] => 'Frequency converter, orthogonal demodulator and orthogonal modulator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622434 | Frequency converter, orthogonal demodulator and orthogonal modulator | Jul 20, 2003 | Issued |
Array
(
[id] => 7120695
[patent_doc_number] => 20050012524
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[patent_title] => 'PLL lock detection circuit using edge detection'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622627 | PLL lock detection circuit using edge detection | Jul 16, 2003 | Issued |
Array
(
[id] => 997040
[patent_doc_number] => 06914464
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[patent_title] => 'Phase locked loop circuit using fractional frequency divider'
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[firstpage_image] =>[orig_patent_app_number] => 10620509
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/620509 | Phase locked loop circuit using fractional frequency divider | Jul 15, 2003 | Issued |
Array
(
[id] => 1125811
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[patent_title] => 'System and method for generating minimum on-time pulses'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/620100 | System and method for generating minimum on-time pulses | Jul 13, 2003 | Issued |
Array
(
[id] => 7121242
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[patent_title] => 'Slew rate at buffers by isolating predriver from driver'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/504366 | Direct conversion receiver using vertical bipolar junction transistor available in deep n-well CMOS technology | Jul 10, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/617080 | Conditional clock buffer circuit | Jul 9, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/615992 | Frequency synthesizer | Jul 9, 2003 | Issued |