Search

Qing Yuan Wu

Examiner (ID: 12021)

Most Active Art Unit
2199
Art Unit(s)
2199, 2194, 2127, 2196, 2126
Total Applications
1028
Issued Applications
876
Pending Applications
65
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4210852 [patent_doc_number] => 06044410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'System for data transfer where multi-word data transmission from industrial controller to I/O module is performed using I/O image table-based handshaking protocol' [patent_app_type] => 1 [patent_app_number] => 9/085942 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3548 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044410.pdf [firstpage_image] =>[orig_patent_app_number] => 085942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085942
System for data transfer where multi-word data transmission from industrial controller to I/O module is performed using I/O image table-based handshaking protocol May 27, 1998 Issued
Array ( [id] => 4259554 [patent_doc_number] => 06092139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Passive backplane capable of being configured to a variable data path width corresponding to a data size of the pluggable CPU board' [patent_app_type] => 1 [patent_app_number] => 9/083083 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092139.pdf [firstpage_image] =>[orig_patent_app_number] => 083083 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083083
Passive backplane capable of being configured to a variable data path width corresponding to a data size of the pluggable CPU board May 21, 1998 Issued
Array ( [id] => 4198682 [patent_doc_number] => 06038616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Computer system with remotely located interface where signals are encoded at the computer system, transferred through a 4-wire cable, and decoded at the interface' [patent_app_type] => 1 [patent_app_number] => 9/072320 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7194 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038616.pdf [firstpage_image] =>[orig_patent_app_number] => 072320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/072320
Computer system with remotely located interface where signals are encoded at the computer system, transferred through a 4-wire cable, and decoded at the interface May 3, 1998 Issued
Array ( [id] => 4210951 [patent_doc_number] => 06044417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'System for controlling operational characteristics of buffer group where capture registers receive control signals in parallel and update registers transfer control signals to buffer group' [patent_app_type] => 1 [patent_app_number] => 9/002140 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6069 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044417.pdf [firstpage_image] =>[orig_patent_app_number] => 002140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002140
System for controlling operational characteristics of buffer group where capture registers receive control signals in parallel and update registers transfer control signals to buffer group Dec 30, 1997 Issued
Array ( [id] => 3968865 [patent_doc_number] => 05948079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'System for non-sequential transfer of data packet portions with respective portion descriptions from a computer network peripheral device to host memory' [patent_app_type] => 1 [patent_app_number] => 8/994807 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3114 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948079.pdf [firstpage_image] =>[orig_patent_app_number] => 994807 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994807
System for non-sequential transfer of data packet portions with respective portion descriptions from a computer network peripheral device to host memory Dec 18, 1997 Issued
Array ( [id] => 4121204 [patent_doc_number] => 06023736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'System for dynamically configuring I/O device adapters where a function configuration register contains ready/not ready flags corresponding to each I/O device adapter' [patent_app_type] => 1 [patent_app_number] => 8/995157 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 6 [patent_no_of_words] => 6005 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023736.pdf [firstpage_image] =>[orig_patent_app_number] => 995157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995157
System for dynamically configuring I/O device adapters where a function configuration register contains ready/not ready flags corresponding to each I/O device adapter Dec 18, 1997 Issued
Array ( [id] => 4225505 [patent_doc_number] => 06029211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'PC card capable multiple functions and corresponding card information structures (CIS) where switch setting element selects CIS to read out based on selection signal' [patent_app_type] => 1 [patent_app_number] => 8/984433 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4936 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029211.pdf [firstpage_image] =>[orig_patent_app_number] => 984433 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984433
PC card capable multiple functions and corresponding card information structures (CIS) where switch setting element selects CIS to read out based on selection signal Dec 2, 1997 Issued
Array ( [id] => 4223531 [patent_doc_number] => 06078970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'System for determining adapter interrupt status where interrupt is sent to host after operating status stored in register is shadowed to host memory' [patent_app_type] => 1 [patent_app_number] => 8/951157 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 9 [patent_no_of_words] => 8823 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078970.pdf [firstpage_image] =>[orig_patent_app_number] => 951157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/951157
System for determining adapter interrupt status where interrupt is sent to host after operating status stored in register is shadowed to host memory Oct 14, 1997 Issued
Array ( [id] => 3915872 [patent_doc_number] => 05951658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'System for dynamic allocation of I/O buffers for VSAM access method based upon intended record access where performance information regarding access is stored in memory' [patent_app_type] => 1 [patent_app_number] => 8/937497 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7312 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951658.pdf [firstpage_image] =>[orig_patent_app_number] => 937497 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937497
System for dynamic allocation of I/O buffers for VSAM access method based upon intended record access where performance information regarding access is stored in memory Sep 24, 1997 Issued
Array ( [id] => 4057140 [patent_doc_number] => 05996033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Data compression device comprising input connector for connecting to game player system, output connector for connecting to memory card, and virtual memory page switch' [patent_app_type] => 1 [patent_app_number] => 8/923606 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1048 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996033.pdf [firstpage_image] =>[orig_patent_app_number] => 923606 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923606
Data compression device comprising input connector for connecting to game player system, output connector for connecting to memory card, and virtual memory page switch Sep 3, 1997 Issued
Array ( [id] => 4085093 [patent_doc_number] => 06009490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'System having plurality of nodes with respective memories and an arbiter for performing arbitration of connection line use for transfer of data between nodes' [patent_app_type] => 1 [patent_app_number] => 8/915318 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4687 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009490.pdf [firstpage_image] =>[orig_patent_app_number] => 915318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915318
System having plurality of nodes with respective memories and an arbiter for performing arbitration of connection line use for transfer of data between nodes Aug 19, 1997 Issued
Array ( [id] => 3961208 [patent_doc_number] => 05974486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Universal serial bus device controller comprising a FIFO associated with a plurality of endpoints and a memory for storing an identifier of a current endpoint' [patent_app_type] => 1 [patent_app_number] => 8/909988 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 9095 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974486.pdf [firstpage_image] =>[orig_patent_app_number] => 909988 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/909988
Universal serial bus device controller comprising a FIFO associated with a plurality of endpoints and a memory for storing an identifier of a current endpoint Aug 11, 1997 Issued
Array ( [id] => 3961120 [patent_doc_number] => 05974479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'System for executing, canceling, or suspending a DMA transfer based upon internal priority comparison between a DMA transfer and an interrupt request' [patent_app_type] => 1 [patent_app_number] => 8/908978 [patent_app_country] => US [patent_app_date] => 1997-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4826 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974479.pdf [firstpage_image] =>[orig_patent_app_number] => 908978 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908978
System for executing, canceling, or suspending a DMA transfer based upon internal priority comparison between a DMA transfer and an interrupt request Aug 7, 1997 Issued
Array ( [id] => 4036550 [patent_doc_number] => 05968141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'System for selectively upgrading firmware code for optical disk drive via ATA/IDE interface based on host system programming enable signal' [patent_app_type] => 1 [patent_app_number] => 8/904541 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5877 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968141.pdf [firstpage_image] =>[orig_patent_app_number] => 904541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904541
System for selectively upgrading firmware code for optical disk drive via ATA/IDE interface based on host system programming enable signal Aug 3, 1997 Issued
Array ( [id] => 3915828 [patent_doc_number] => 05951655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'External storage subsystem having independent access paths for permitting independent access from a host and a storage device to respective cache memories' [patent_app_type] => 1 [patent_app_number] => 8/902362 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3340 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951655.pdf [firstpage_image] =>[orig_patent_app_number] => 902362 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902362
External storage subsystem having independent access paths for permitting independent access from a host and a storage device to respective cache memories Jul 28, 1997 Issued
Array ( [id] => 4138349 [patent_doc_number] => 06073190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair' [patent_app_type] => 1 [patent_app_number] => 8/896938 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 13 [patent_no_of_words] => 14611 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073190.pdf [firstpage_image] =>[orig_patent_app_number] => 896938 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896938
System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair Jul 17, 1997 Issued
08/884955 NOVEL COMPUTER PLATFORM CONNECTION UTILIZING VIRTUAL SYSTEM BUS Jun 29, 1997 Abandoned
Array ( [id] => 4068625 [patent_doc_number] => 05933656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'System for interfacing host computer to multiple peripheral devices using daisy-chainable bus and federated computational input/output circuit card assemblies' [patent_app_type] => 1 [patent_app_number] => 8/878472 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3814 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933656.pdf [firstpage_image] =>[orig_patent_app_number] => 878472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878472
System for interfacing host computer to multiple peripheral devices using daisy-chainable bus and federated computational input/output circuit card assemblies Jun 17, 1997 Issued
Array ( [id] => 3971193 [patent_doc_number] => 06000018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'System for aligning control words for identifying boundaries of headerless data sectors using automatic incrementing and discarding of data frame numbers' [patent_app_type] => 1 [patent_app_number] => 8/877115 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10948 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000018.pdf [firstpage_image] =>[orig_patent_app_number] => 877115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877115
System for aligning control words for identifying boundaries of headerless data sectors using automatic incrementing and discarding of data frame numbers Jun 16, 1997 Issued
Array ( [id] => 3973023 [patent_doc_number] => 05978863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Host adaptor comprising a status switching circuit which couples an output line to a function input line in response to a function enable line signal' [patent_app_type] => 1 [patent_app_number] => 8/876539 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7744 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978863.pdf [firstpage_image] =>[orig_patent_app_number] => 876539 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876539
Host adaptor comprising a status switching circuit which couples an output line to a function input line in response to a function enable line signal Jun 8, 1997 Issued
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