Search

Qing Yuan Wu

Examiner (ID: 12021)

Most Active Art Unit
2199
Art Unit(s)
2199, 2194, 2127, 2196, 2126
Total Applications
1028
Issued Applications
876
Pending Applications
65
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3807574 [patent_doc_number] => 05842040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Policy caching method and apparatus for use in a communication device based on contents of one data unit in a subset of related data units' [patent_app_type] => 1 [patent_app_number] => 8/666638 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6969 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/842/05842040.pdf [firstpage_image] =>[orig_patent_app_number] => 666638 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/666638
Policy caching method and apparatus for use in a communication device based on contents of one data unit in a subset of related data units Jun 17, 1996 Issued
Array ( [id] => 4099635 [patent_doc_number] => 06055590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size' [patent_app_type] => 1 [patent_app_number] => 8/658533 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 127 [patent_figures_cnt] => 134 [patent_no_of_words] => 71061 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055590.pdf [firstpage_image] =>[orig_patent_app_number] => 658533 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658533
Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size Jun 4, 1996 Issued
Array ( [id] => 3966055 [patent_doc_number] => 05956521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'System for universal electronic mail delivery where messaging devices are notified using a particular dialing, ringing, and hanging-up pattern' [patent_app_type] => 1 [patent_app_number] => 8/656651 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9031 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956521.pdf [firstpage_image] =>[orig_patent_app_number] => 656651 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656651
System for universal electronic mail delivery where messaging devices are notified using a particular dialing, ringing, and hanging-up pattern May 30, 1996 Issued
Array ( [id] => 4014951 [patent_doc_number] => 05925109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'System for I/O management where I/O operations are determined to be direct or indirect based on hardware coupling manners and/or program privilege modes' [patent_app_type] => 1 [patent_app_number] => 8/630387 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7180 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925109.pdf [firstpage_image] =>[orig_patent_app_number] => 630387 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630387
System for I/O management where I/O operations are determined to be direct or indirect based on hardware coupling manners and/or program privilege modes Apr 9, 1996 Issued
Array ( [id] => 3779519 [patent_doc_number] => 05845149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Industrial controller with I/O mapping table for linking software addresses to physical network addresses' [patent_app_type] => 1 [patent_app_number] => 8/630394 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5906 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845149.pdf [firstpage_image] =>[orig_patent_app_number] => 630394 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630394
Industrial controller with I/O mapping table for linking software addresses to physical network addresses Apr 9, 1996 Issued
Array ( [id] => 4082252 [patent_doc_number] => 05867736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Methods for simplified integration of host based storage array control functions using read and write operations on a storage array control port' [patent_app_type] => 1 [patent_app_number] => 8/624235 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7952 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867736.pdf [firstpage_image] =>[orig_patent_app_number] => 624235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/624235
Methods for simplified integration of host based storage array control functions using read and write operations on a storage array control port Mar 28, 1996 Issued
Array ( [id] => 4042747 [patent_doc_number] => 05903774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'External network network interface device without interim storage connected to high-speed serial bus with low latency and high transmission rate' [patent_app_type] => 1 [patent_app_number] => 8/624999 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2134 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903774.pdf [firstpage_image] =>[orig_patent_app_number] => 624999 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/624999
External network network interface device without interim storage connected to high-speed serial bus with low latency and high transmission rate Mar 28, 1996 Issued
Array ( [id] => 3918149 [patent_doc_number] => 05898815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency' [patent_app_type] => 1 [patent_app_number] => 8/600781 [patent_app_country] => US [patent_app_date] => 1996-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 16 [patent_no_of_words] => 5800 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898815.pdf [firstpage_image] =>[orig_patent_app_number] => 600781 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/600781
I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency Feb 12, 1996 Issued
Array ( [id] => 4030459 [patent_doc_number] => 05907719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Communication interface unit employing two multiplexer circuits and control logic for performing parallel-to-serial data conversion of a selected asynchronous protocol' [patent_app_type] => 1 [patent_app_number] => 8/589663 [patent_app_country] => US [patent_app_date] => 1996-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4762 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907719.pdf [firstpage_image] =>[orig_patent_app_number] => 589663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/589663
Communication interface unit employing two multiplexer circuits and control logic for performing parallel-to-serial data conversion of a selected asynchronous protocol Jan 21, 1996 Issued
Array ( [id] => 3813813 [patent_doc_number] => 05828900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'International multiple-byte character generator support in application sharing which distinguishes guest keyboard input from host key board and bypassing execution of the generator module when guest keyboard input is determined' [patent_app_type] => 1 [patent_app_number] => 8/579722 [patent_app_country] => US [patent_app_date] => 1996-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4061 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828900.pdf [firstpage_image] =>[orig_patent_app_number] => 579722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/579722
International multiple-byte character generator support in application sharing which distinguishes guest keyboard input from host key board and bypassing execution of the generator module when guest keyboard input is determined Jan 2, 1996 Issued
Array ( [id] => 4025881 [patent_doc_number] => 05941959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'System for transferring a data stream to a requestor without copying data segments to each one of multiple data source/sinks during data stream building' [patent_app_type] => 1 [patent_app_number] => 8/578409 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11713 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 490 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941959.pdf [firstpage_image] =>[orig_patent_app_number] => 578409 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/578409
System for transferring a data stream to a requestor without copying data segments to each one of multiple data source/sinks during data stream building Dec 19, 1995 Issued
Array ( [id] => 4065569 [patent_doc_number] => 05870627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'System for managing direct memory access transfer in a multi-channel system using circular descriptor queue, descriptor FIFO, and receive status queue' [patent_app_type] => 1 [patent_app_number] => 8/576868 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6142 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870627.pdf [firstpage_image] =>[orig_patent_app_number] => 576868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/576868
System for managing direct memory access transfer in a multi-channel system using circular descriptor queue, descriptor FIFO, and receive status queue Dec 19, 1995 Issued
Array ( [id] => 4069003 [patent_doc_number] => 05970255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly' [patent_app_type] => 1 [patent_app_number] => 8/543649 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5181 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970255.pdf [firstpage_image] =>[orig_patent_app_number] => 543649 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543649
System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly Oct 15, 1995 Issued
Array ( [id] => 4195347 [patent_doc_number] => 06038400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Self-configuring interface circuitry, including circuitry for identifying a protocol used to send signals to the interface circuitry, and circuitry for receiving the signals using the identified protocol' [patent_app_type] => 1 [patent_app_number] => 8/534336 [patent_app_country] => US [patent_app_date] => 1995-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8522 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038400.pdf [firstpage_image] =>[orig_patent_app_number] => 534336 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534336
Self-configuring interface circuitry, including circuitry for identifying a protocol used to send signals to the interface circuitry, and circuitry for receiving the signals using the identified protocol Sep 26, 1995 Issued
Array ( [id] => 3827163 [patent_doc_number] => 05832303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Large scale interconnecting switch using communication controller groups with multiple input-to-one output signal lines and adaptable crossbar unit using plurality of selectors' [patent_app_type] => 1 [patent_app_number] => 8/516392 [patent_app_country] => US [patent_app_date] => 1995-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5377 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832303.pdf [firstpage_image] =>[orig_patent_app_number] => 516392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/516392
Large scale interconnecting switch using communication controller groups with multiple input-to-one output signal lines and adaptable crossbar unit using plurality of selectors Aug 16, 1995 Issued
Array ( [id] => 4038062 [patent_doc_number] => 05926651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Output buffer with current paths having different current carrying characteristics for providing programmable slew rate and signal strength' [patent_app_type] => 1 [patent_app_number] => 8/508668 [patent_app_country] => US [patent_app_date] => 1995-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926651.pdf [firstpage_image] =>[orig_patent_app_number] => 508668 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/508668
Output buffer with current paths having different current carrying characteristics for providing programmable slew rate and signal strength Jul 27, 1995 Issued
Array ( [id] => 3944038 [patent_doc_number] => 05878275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Information processing apparatus which discriminates whether or not input information is stored in memory and controlling the switching from a first control program to a second control program' [patent_app_type] => 1 [patent_app_number] => 8/280588 [patent_app_country] => US [patent_app_date] => 1994-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 9488 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878275.pdf [firstpage_image] =>[orig_patent_app_number] => 280588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280588
Information processing apparatus which discriminates whether or not input information is stored in memory and controlling the switching from a first control program to a second control program Jul 25, 1994 Issued
Array ( [id] => 4077353 [patent_doc_number] => RE036653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Search/retrieval system' [patent_app_type] => 2 [patent_app_number] => 7/504679 [patent_app_country] => US [patent_app_date] => 1990-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 7221 [patent_no_of_claims] => 96 [patent_no_of_ind_claims] => 90 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036653.pdf [firstpage_image] =>[orig_patent_app_number] => 504679 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/504679
Search/retrieval system Apr 3, 1990 Issued
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