Search

Quang Pham

Examiner (ID: 17839, Phone: (571)270-3668 , Office: P/2684 )

Most Active Art Unit
2684
Art Unit(s)
2685, 2612, 2684
Total Applications
836
Issued Applications
452
Pending Applications
74
Abandoned Applications
327

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6762994 [patent_doc_number] => 20030126356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => ' Memory system having synchronous-link DRAM (SLDRAM) devices and controller' [patent_app_type] => new [patent_app_number] => 10/176327 [patent_app_country] => US [patent_app_date] => 2002-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 30268 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126356.pdf [firstpage_image] =>[orig_patent_app_number] => 10176327 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/176327
Memory system having synchronous-link DRAM (SLDRAM) devices and controller Jun 18, 2002 Abandoned
Array ( [id] => 633368 [patent_doc_number] => 07133999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Method and system for local memory addressing in single instruction, multiple data computer system' [patent_app_type] => utility [patent_app_number] => 10/171049 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4543 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/133/07133999.pdf [firstpage_image] =>[orig_patent_app_number] => 10171049 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/171049
Method and system for local memory addressing in single instruction, multiple data computer system Jun 11, 2002 Issued
Array ( [id] => 6746624 [patent_doc_number] => 20030023807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Disk drive device and control device thereof' [patent_app_type] => new [patent_app_number] => 10/166097 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11280 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023807.pdf [firstpage_image] =>[orig_patent_app_number] => 10166097 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/166097
Disk drive device and control device thereof Jun 10, 2002 Abandoned
Array ( [id] => 6265367 [patent_doc_number] => 20020188814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Non-volatile storage device and rewrite control method thereof' [patent_app_type] => new [patent_app_number] => 10/164657 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13352 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188814.pdf [firstpage_image] =>[orig_patent_app_number] => 10164657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164657
Non-volatile storage device and rewrite control method thereof Jun 5, 2002 Issued
Array ( [id] => 6771283 [patent_doc_number] => 20030217223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Combined command set' [patent_app_type] => new [patent_app_number] => 10/145760 [patent_app_country] => US [patent_app_date] => 2002-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3812 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20030217223.pdf [firstpage_image] =>[orig_patent_app_number] => 10145760 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/145760
Combined command set May 13, 2002 Abandoned
Array ( [id] => 1415646 [patent_doc_number] => 06549981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Disk array system with controllers that automate host side of ATA interface' [patent_app_type] => B2 [patent_app_number] => 10/142562 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12332 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549981.pdf [firstpage_image] =>[orig_patent_app_number] => 10142562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/142562
Disk array system with controllers that automate host side of ATA interface May 8, 2002 Issued
Array ( [id] => 1082980 [patent_doc_number] => 06836821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'System and method for providing graph structuring for layered virtual volumes' [patent_app_type] => B2 [patent_app_number] => 10/127870 [patent_app_country] => US [patent_app_date] => 2002-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836821.pdf [firstpage_image] =>[orig_patent_app_number] => 10127870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127870
System and method for providing graph structuring for layered virtual volumes Apr 22, 2002 Issued
Array ( [id] => 6810456 [patent_doc_number] => 20030200395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Interleaved n-way set-associative external cache' [patent_app_type] => new [patent_app_number] => 10/127172 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8514 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200395.pdf [firstpage_image] =>[orig_patent_app_number] => 10127172 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127172
Interleaved n-way set-associative external cache Apr 21, 2002 Issued
Array ( [id] => 6810465 [patent_doc_number] => 20030200404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'N-way set-associative external cache with standard DDR memory devices' [patent_app_type] => new [patent_app_number] => 10/127173 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8825 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200404.pdf [firstpage_image] =>[orig_patent_app_number] => 10127173 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127173
N-way set-associative external cache with standard DDR memory devices Apr 21, 2002 Issued
Array ( [id] => 6810450 [patent_doc_number] => 20030200389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'System and method of cache management for storage controllers' [patent_app_type] => new [patent_app_number] => 10/125712 [patent_app_country] => US [patent_app_date] => 2002-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200389.pdf [firstpage_image] =>[orig_patent_app_number] => 10125712 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/125712
System and method of cache management for storage controllers Apr 17, 2002 Issued
Array ( [id] => 6780019 [patent_doc_number] => 20030051101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Cache for large-object real-time latency elimination' [patent_app_type] => new [patent_app_number] => 10/125050 [patent_app_country] => US [patent_app_date] => 2002-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5711 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20030051101.pdf [firstpage_image] =>[orig_patent_app_number] => 10125050 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/125050
Cache for large-object real-time latency elimination Apr 17, 2002 Issued
Array ( [id] => 6731931 [patent_doc_number] => 20030188121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Efficiency in a memory management system' [patent_app_type] => new [patent_app_number] => 10/106025 [patent_app_country] => US [patent_app_date] => 2002-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6901 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20030188121.pdf [firstpage_image] =>[orig_patent_app_number] => 10106025 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/106025
Efficiency in a memory management system Mar 26, 2002 Issued
Array ( [id] => 6731901 [patent_doc_number] => 20030188091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Exchanging operation parameters between a data storage device and a controller' [patent_app_type] => new [patent_app_number] => 10/107560 [patent_app_country] => US [patent_app_date] => 2002-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6125 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20030188091.pdf [firstpage_image] =>[orig_patent_app_number] => 10107560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/107560
Exchanging operation parameters between a data storage device and a controller Mar 26, 2002 Issued
Array ( [id] => 1431388 [patent_doc_number] => 06519673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Multi-bank, fault-tolerant, high-performance memory addressing system and method' [patent_app_type] => B1 [patent_app_number] => 10/107079 [patent_app_country] => US [patent_app_date] => 2002-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 41 [patent_no_of_words] => 11557 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519673.pdf [firstpage_image] =>[orig_patent_app_number] => 10107079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/107079
Multi-bank, fault-tolerant, high-performance memory addressing system and method Mar 25, 2002 Issued
Array ( [id] => 6871575 [patent_doc_number] => 20030084265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Preemptive memory-block splitting' [patent_app_type] => new [patent_app_number] => 10/103637 [patent_app_country] => US [patent_app_date] => 2002-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7006 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20030084265.pdf [firstpage_image] =>[orig_patent_app_number] => 10103637 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/103637
Preemptive memory-block splitting Mar 20, 2002 Issued
Array ( [id] => 5990700 [patent_doc_number] => 20020099921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'System, method, and apparatus for providing linearly scalable dynamic memory management in a multiprocessing system' [patent_app_type] => new [patent_app_number] => 10/098398 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4383 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099921.pdf [firstpage_image] =>[orig_patent_app_number] => 10098398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/098398
System, method, and apparatus for providing linearly scalable dynamic memory management in a multiprocessing system Mar 14, 2002 Issued
Array ( [id] => 757614 [patent_doc_number] => 07024518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Dual-port buffer-to-memory interface' [patent_app_type] => utility [patent_app_number] => 10/100312 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5796 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024518.pdf [firstpage_image] =>[orig_patent_app_number] => 10100312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/100312
Dual-port buffer-to-memory interface Mar 12, 2002 Issued
Array ( [id] => 6554397 [patent_doc_number] => 20020194431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Multi-level cache system' [patent_app_type] => new [patent_app_number] => 10/094261 [patent_app_country] => US [patent_app_date] => 2002-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4482 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194431.pdf [firstpage_image] =>[orig_patent_app_number] => 10094261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/094261
Multi-level cache system with simplified miss/replacement control Mar 7, 2002 Issued
Array ( [id] => 1043168 [patent_doc_number] => 06871264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/092645 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2488 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/871/06871264.pdf [firstpage_image] =>[orig_patent_app_number] => 10092645 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092645
System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits Mar 5, 2002 Issued
Array ( [id] => 6836106 [patent_doc_number] => 20030163652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Storage management integrated system and storage control method for storage management integrated system' [patent_app_type] => new [patent_app_number] => 10/085036 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12900 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163652.pdf [firstpage_image] =>[orig_patent_app_number] => 10085036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/085036
Storage management integrated system and storage control method for storage management integrated system Feb 28, 2002 Issued
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