Quovaunda Jefferson

Array ( [id] => 16781593 [patent_doc_number] => 20210118672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => ATOMIC LAYER DEPOSITION OF INDIUM GALLIUM ZINC OXIDE [patent_app_type] => utility [patent_app_number] => 17/072525 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18431614 [patent_doc_number] => 11676843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => System and method for connecting electronic assemblies [patent_app_type] => utility [patent_app_number] => 17/642533 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 16402 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17642533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17509451 [patent_doc_number] => 20220102554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => GATE AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 17/033453 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18481172 [patent_doc_number] => 11694926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Barrier free interface between beol interconnects [patent_app_type] => utility [patent_app_number] => 17/032407 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 9202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16586107 [patent_doc_number] => 20210020509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING CONTACT PLUGS [patent_app_type] => utility [patent_app_number] => 17/031279 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17485954 [patent_doc_number] => 20220093458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => TECHNIQUES FOR VOID-FREE MATERIAL DEPOSITIONS [patent_app_type] => utility [patent_app_number] => 17/028259 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18669950 [patent_doc_number] => 11776862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Lid structure and semiconductor device package including the same [patent_app_type] => utility [patent_app_number] => 17/027408 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5761 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18431585 [patent_doc_number] => 11676813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Doping semiconductor films [patent_app_type] => utility [patent_app_number] => 17/025009 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6119 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16559983 [patent_doc_number] => 20210005132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/022103 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16966126 [patent_doc_number] => 20210217625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => METHODS OF CUTTING A FINE PATTERN, METHODS OF FORMING ACTIVE PATTERNS USING THE SAME, AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/022208 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19341494 [patent_doc_number] => 12051691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Planar and non-planar FET-based electrostatic discharge protection devices [patent_app_type] => utility [patent_app_number] => 17/020507 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 7037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16723805 [patent_doc_number] => 20210090952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => Fully Self-Aligned Via [patent_app_type] => utility [patent_app_number] => 17/019909 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16528711 [patent_doc_number] => 20200402792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => WAFER TREATMENT FOR ACHIEVING DEFECT-FREE SELF-ASSEMBLED MONOLAYERS [patent_app_type] => utility [patent_app_number] => 17/014975 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17085424 [patent_doc_number] => 20210280431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => PATTERN FORMATION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/010989 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20484193 [patent_doc_number] => 12532674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Methods and apparatus for depositing a chalcogenide film and structures including the film [patent_app_type] => utility [patent_app_number] => 17/007221 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5976 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17448210 [patent_doc_number] => 20220068715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => ENHANCED ETCH RESISTANCE FOR INSULATOR LAYERS IMPLANTED WITH LOW ENERGY IONS [patent_app_type] => utility [patent_app_number] => 17/006428 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17448410 [patent_doc_number] => 20220068915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => GATE MATERIAL-BASED CAPACITOR AND RESISTOR STRUCTURES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/006265 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16456271 [patent_doc_number] => 20200365697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/987909 [patent_app_country] => US [patent_app_date] => 2020-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16987909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17607105 [patent_doc_number] => 11335597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Method for forming a buried metal line [patent_app_type] => utility [patent_app_number] => 16/945858 [patent_app_country] => US [patent_app_date] => 2020-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 7073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19444400 [patent_doc_number] => 12094689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Switchable delivery for semiconductor processing system [patent_app_type] => utility [patent_app_number] => 16/932794 [patent_app_country] => US [patent_app_date] => 2020-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7475 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932794 [rel_patent_id] =>[rel_patent_doc_number] =>)