Search

Quovaunda Jefferson

Examiner (ID: 11007, Phone: (571)272-5051 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2823, 2899
Total Applications
1137
Issued Applications
831
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18263097 [patent_doc_number] => 11610806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Multilayer stack of semiconductor-on-insulator type, associated production process, and radio frequency module comprising it [patent_app_type] => utility [patent_app_number] => 17/124142 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 9488 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124142 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124142
Multilayer stack of semiconductor-on-insulator type, associated production process, and radio frequency module comprising it Dec 15, 2020 Issued
Array ( [id] => 16781899 [patent_doc_number] => 20210118978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => TRENCH CAPACITOR AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/116823 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116823
Trench capacitor and method of forming the same Dec 8, 2020 Issued
Array ( [id] => 16888921 [patent_doc_number] => 20210175118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SELF-ASSEMBLED MONOLAYERS AS SACRIFICIAL CAPPING LAYERS [patent_app_type] => utility [patent_app_number] => 17/115231 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115231
Self-assembled monolayers as sacrificial capping layers Dec 7, 2020 Issued
Array ( [id] => 17630603 [patent_doc_number] => 20220165618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => 3D BONDED SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/103902 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103902
3D BONDED SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME Nov 23, 2020 Abandoned
Array ( [id] => 18165735 [patent_doc_number] => 20230032336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => METHOD FOR BONDING TWO SUBSTRATES [patent_app_type] => utility [patent_app_number] => 17/756431 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17756431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/756431
Method for bonding two substrates Nov 23, 2020 Issued
Array ( [id] => 16689953 [patent_doc_number] => 20210072430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/102204 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102204 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102204
SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD, AND ELECTRONIC APPARATUS Nov 22, 2020 Abandoned
Array ( [id] => 16692276 [patent_doc_number] => 20210074755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => CAPPING STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORS [patent_app_type] => utility [patent_app_number] => 16/952384 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952384
Capping structure to reduce dark current in image sensors Nov 18, 2020 Issued
Array ( [id] => 17615323 [patent_doc_number] => 20220157603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SPIN COATING PROCESS AND APPARATUS WITH ULTRASONIC VISCOSITY CONTROL [patent_app_type] => utility [patent_app_number] => 16/951291 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951291 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951291
Spin coating process and apparatus with ultrasonic viscosity control Nov 17, 2020 Issued
Array ( [id] => 18431730 [patent_doc_number] => 11676961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Semiconductor device with low noise transistor and low temperature coefficient resistor [patent_app_type] => utility [patent_app_number] => 17/086421 [patent_app_country] => US [patent_app_date] => 2020-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086421 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/086421
Semiconductor device with low noise transistor and low temperature coefficient resistor Oct 31, 2020 Issued
Array ( [id] => 18782194 [patent_doc_number] => 11823960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Method for forming semiconductor structure with high aspect ratio [patent_app_type] => utility [patent_app_number] => 17/079787 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079787
Method for forming semiconductor structure with high aspect ratio Oct 25, 2020 Issued
Array ( [id] => 18688533 [patent_doc_number] => 11784279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Method and device for producing a photovoltaic element with stabilised efficiency [patent_app_type] => utility [patent_app_number] => 17/077995 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 11600 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077995
Method and device for producing a photovoltaic element with stabilised efficiency Oct 21, 2020 Issued
Array ( [id] => 16631628 [patent_doc_number] => 20210050281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => Surface Treatment Method and Apparatus for Semiconductor Packaging [patent_app_type] => utility [patent_app_number] => 17/073937 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/073937
Surface treatment method and apparatus for semiconductor packaging Oct 18, 2020 Issued
Array ( [id] => 16781593 [patent_doc_number] => 20210118672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => ATOMIC LAYER DEPOSITION OF INDIUM GALLIUM ZINC OXIDE [patent_app_type] => utility [patent_app_number] => 17/072525 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072525
Atomic layer deposition of indium gallium zinc oxide Oct 15, 2020 Issued
Array ( [id] => 18431614 [patent_doc_number] => 11676843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => System and method for connecting electronic assemblies [patent_app_type] => utility [patent_app_number] => 17/642533 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 16402 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17642533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/642533
System and method for connecting electronic assemblies Oct 1, 2020 Issued
Array ( [id] => 18481172 [patent_doc_number] => 11694926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Barrier free interface between beol interconnects [patent_app_type] => utility [patent_app_number] => 17/032407 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 9202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/032407
Barrier free interface between beol interconnects Sep 24, 2020 Issued
Array ( [id] => 17509451 [patent_doc_number] => 20220102554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => GATE AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 17/033453 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033453
GATE AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Sep 24, 2020 Pending
Array ( [id] => 16586107 [patent_doc_number] => 20210020509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING CONTACT PLUGS [patent_app_type] => utility [patent_app_number] => 17/031279 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031279
Semiconductor devices including contact plugs Sep 23, 2020 Issued
Array ( [id] => 17485954 [patent_doc_number] => 20220093458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => TECHNIQUES FOR VOID-FREE MATERIAL DEPOSITIONS [patent_app_type] => utility [patent_app_number] => 17/028259 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028259
Techniques for void-free material depositions Sep 21, 2020 Issued
Array ( [id] => 18669950 [patent_doc_number] => 11776862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Lid structure and semiconductor device package including the same [patent_app_type] => utility [patent_app_number] => 17/027408 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5761 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027408
Lid structure and semiconductor device package including the same Sep 20, 2020 Issued
Array ( [id] => 18431585 [patent_doc_number] => 11676813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Doping semiconductor films [patent_app_type] => utility [patent_app_number] => 17/025009 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6119 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025009 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025009
Doping semiconductor films Sep 17, 2020 Issued
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