
Quovaunda Jefferson
Examiner (ID: 11007, Phone: (571)272-5051 , Office: P/2899 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2823, 2899 |
| Total Applications | 1137 |
| Issued Applications | 831 |
| Pending Applications | 88 |
| Abandoned Applications | 234 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14875703
[patent_doc_number] => 20190288093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-19
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/429176
[patent_app_country] => US
[patent_app_date] => 2019-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 48933
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429176
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/429176 | Semiconductor device and method for manufacturing the same | Jun 2, 2019 | Issued |
Array
(
[id] => 16765490
[patent_doc_number] => 20210111072
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-15
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/057828
[patent_app_country] => US
[patent_app_date] => 2019-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12154
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17057828
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/057828 | Method for manufacturing semiconductor device | May 26, 2019 | Issued |
Array
(
[id] => 19314360
[patent_doc_number] => 12040185
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-16
[patent_title] => Solution-based deposition method for preparing semiconducting thin films via dispersed particle self-assembly at a liquid-liquid interface
[patent_app_type] => utility
[patent_app_number] => 17/613324
[patent_app_country] => US
[patent_app_date] => 2019-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 7806
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17613324
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/613324 | Solution-based deposition method for preparing semiconducting thin films via dispersed particle self-assembly at a liquid-liquid interface | May 21, 2019 | Issued |
Array
(
[id] => 17978616
[patent_doc_number] => 11495488
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-08
[patent_title] => Method for manufacturing bonded SOI wafer and bonded SOI wafer
[patent_app_type] => utility
[patent_app_number] => 16/973575
[patent_app_country] => US
[patent_app_date] => 2019-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4786
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16973575
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/973575 | Method for manufacturing bonded SOI wafer and bonded SOI wafer | May 13, 2019 | Issued |
Array
(
[id] => 14784709
[patent_doc_number] => 20190267252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 16/406899
[patent_app_country] => US
[patent_app_date] => 2019-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4922
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406899
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/406899 | Semiconductor component and method of manufacture | May 7, 2019 | Issued |
Array
(
[id] => 16234082
[patent_doc_number] => 10741646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-11
[patent_title] => Field-effect transistors having contacts to 2D material active region
[patent_app_type] => utility
[patent_app_number] => 16/404289
[patent_app_country] => US
[patent_app_date] => 2019-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 12098
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404289
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/404289 | Field-effect transistors having contacts to 2D material active region | May 5, 2019 | Issued |
Array
(
[id] => 16034913
[patent_doc_number] => 10679888
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-09
[patent_title] => Foundry-agnostic post-processing method for a wafer
[patent_app_type] => utility
[patent_app_number] => 16/403317
[patent_app_country] => US
[patent_app_date] => 2019-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3761
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403317
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/403317 | Foundry-agnostic post-processing method for a wafer | May 2, 2019 | Issued |
Array
(
[id] => 17247023
[patent_doc_number] => 20210366768
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-25
[patent_title] => IMPROVING SUBSTRATE WETTABILITY FOR PLATING OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 17/051432
[patent_app_country] => US
[patent_app_date] => 2019-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6667
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17051432
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/051432 | Improving substrate wettability for plating operations | Apr 28, 2019 | Issued |
Array
(
[id] => 16332272
[patent_doc_number] => 20200303238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => CAPACITANCE REDUCTION FOR SEMICONDUCTOR DEVICES BASED ON WAFER BONDING
[patent_app_type] => utility
[patent_app_number] => 16/358520
[patent_app_country] => US
[patent_app_date] => 2019-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10230
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358520
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/358520 | Capacitance reduction for semiconductor devices based on wafer bonding | Mar 18, 2019 | Issued |
Array
(
[id] => 15823369
[patent_doc_number] => 10636883
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Semiconductor device including a gate trench and a source trench
[patent_app_type] => utility
[patent_app_number] => 16/280242
[patent_app_country] => US
[patent_app_date] => 2019-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 25
[patent_no_of_words] => 6136
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280242
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/280242 | Semiconductor device including a gate trench and a source trench | Feb 19, 2019 | Issued |
Array
(
[id] => 16959087
[patent_doc_number] => 11062969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-13
[patent_title] => Wafer level chip scale package structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 16/261517
[patent_app_country] => US
[patent_app_date] => 2019-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 2565
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261517
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/261517 | Wafer level chip scale package structure and manufacturing method thereof | Jan 28, 2019 | Issued |
Array
(
[id] => 15154851
[patent_doc_number] => 20190355903
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => LAYER COST SCALABLE 3D PHASE CHANGE CROSS-POINT MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/259746
[patent_app_country] => US
[patent_app_date] => 2019-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8883
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259746
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/259746 | Layer cost scalable 3D phase change cross-point memory | Jan 27, 2019 | Issued |
Array
(
[id] => 14677469
[patent_doc_number] => 20190237849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-01
[patent_title] => TFT SUBSTRATE, SCANNED ANTENNA HAVING TFT SUBSTRATE, AND METHOD FOR MANUFACTURING TFT SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 16/259803
[patent_app_country] => US
[patent_app_date] => 2019-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 40718
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259803
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/259803 | TFT substrate, scanned antenna having TFT substrate, and method for manufacturing TFT substrate | Jan 27, 2019 | Issued |
Array
(
[id] => 16210612
[patent_doc_number] => 20200243602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-30
[patent_title] => INTEGRATED CIRCUITS WITH INTEGRATED MEMORY STRUCTURES AND CAPACITORS AND METHODS FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/259549
[patent_app_country] => US
[patent_app_date] => 2019-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4826
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259549
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/259549 | Integrated circuits with integrated memory structures and capacitors and methods for fabricating the same | Jan 27, 2019 | Issued |
Array
(
[id] => 15939669
[patent_doc_number] => 20200161468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-21
[patent_title] => FIN STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/259688
[patent_app_country] => US
[patent_app_date] => 2019-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4091
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259688
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/259688 | Fin structure and method for manufacturing the same | Jan 27, 2019 | Issued |
Array
(
[id] => 16631596
[patent_doc_number] => 20210050249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => REMOVABLE STRUCTURE AND REMOVAL METHOD USING THE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/969346
[patent_app_country] => US
[patent_app_date] => 2019-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5873
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16969346
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/969346 | Removable structure and removal method using the structure | Jan 13, 2019 | Issued |
Array
(
[id] => 16067899
[patent_doc_number] => 10692914
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Implant damage free image sensor and method of the same
[patent_app_type] => utility
[patent_app_number] => 16/241582
[patent_app_country] => US
[patent_app_date] => 2019-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5402
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241582
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/241582 | Implant damage free image sensor and method of the same | Jan 6, 2019 | Issued |
Array
(
[id] => 14284995
[patent_doc_number] => 20190139782
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/235435
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11107
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235435
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/235435 | Nonvolatile semiconductor memory device and method of manufacturing the same | Dec 27, 2018 | Issued |
Array
(
[id] => 16187260
[patent_doc_number] => 10720602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-21
[patent_title] => Display unit
[patent_app_type] => utility
[patent_app_number] => 16/234565
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 9878
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234565
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/234565 | Display unit | Dec 27, 2018 | Issued |
Array
(
[id] => 15955467
[patent_doc_number] => 10665649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-26
[patent_title] => Organic light emitting diode screen and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 16/234355
[patent_app_country] => US
[patent_app_date] => 2018-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4024
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234355
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/234355 | Organic light emitting diode screen and manufacturing method thereof | Dec 26, 2018 | Issued |