Search

Quovaunda Jefferson

Examiner (ID: 11007, Phone: (571)272-5051 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2823, 2899
Total Applications
1137
Issued Applications
831
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18757140 [patent_doc_number] => 20230360597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/223521 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223521 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223521
Display device Jul 17, 2023 Issued
Array ( [id] => 18943442 [patent_doc_number] => 20240038581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => METHOD OF MANUFACTURING SOI WAFER [patent_app_type] => utility [patent_app_number] => 18/353387 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353387
Method of manufacturing SOI wafer Jul 16, 2023 Issued
Array ( [id] => 18882888 [patent_doc_number] => 20240006257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => COMPOSITE SUBSTRATE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/344023 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344023 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344023
COMPOSITE SUBSTRATE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE Jun 28, 2023 Pending
Array ( [id] => 18880564 [patent_doc_number] => 20240003933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => INERTIAL SENSOR, METHOD OF MANUFACTURING INERTIAL SENSOR, AND INERTIAL MEASUREMENT UNIT [patent_app_type] => utility [patent_app_number] => 18/343094 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343094 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343094
INERTIAL SENSOR, METHOD OF MANUFACTURING INERTIAL SENSOR, AND INERTIAL MEASUREMENT UNIT Jun 27, 2023 Pending
Array ( [id] => 18729307 [patent_doc_number] => 20230343603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/343544 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343544
Electronic package and method for fabricating the same Jun 27, 2023 Issued
Array ( [id] => 20013228 [patent_doc_number] => 20250151450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => FABRICATION OF A SEMICONDUCTOR DEVICE INCLUDING A QUANTUM DOT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/341795 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18341795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/341795
FABRICATION OF A SEMICONDUCTOR DEVICE INCLUDING A QUANTUM DOT STRUCTURE Jun 26, 2023 Pending
Array ( [id] => 20692019 [patent_doc_number] => 12622194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Semiconductor structure including devices with different channel lengths, and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/342192 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342192 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342192
Semiconductor structure including devices with different channel lengths, and method for manufacturing the same Jun 26, 2023 Issued
Array ( [id] => 19646432 [patent_doc_number] => 20240420952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => NESTED-LOOP PLASMA ENHANCED ATOMIC LAYER DEPOSITION [patent_app_type] => utility [patent_app_number] => 18/209700 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209700
NESTED-LOOP PLASMA ENHANCED ATOMIC LAYER DEPOSITION Jun 13, 2023 Pending
Array ( [id] => 18903162 [patent_doc_number] => 20240018647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => OXIDATION BARRIERS WITH CVD SOAK PROCESSES [patent_app_type] => utility [patent_app_number] => 18/209257 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209257 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209257
Oxidation barriers with CVD soak processes Jun 12, 2023 Issued
Array ( [id] => 19658471 [patent_doc_number] => 20240425536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => HALOGEN-FREE MOLYBDENUM-CONTAINING PRECURSORS FOR DEPOSITION OF MOLYBDENUM [patent_app_type] => utility [patent_app_number] => 18/209217 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209217 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209217
Halogen-free molybdenum-containing precursors for deposition of molybdenum Jun 12, 2023 Issued
Array ( [id] => 19646476 [patent_doc_number] => 20240420996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SELECTIVE SELF-ASSEMBLED MONOLAYER (SAM) REMOVAL [patent_app_type] => utility [patent_app_number] => 18/209035 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209035
Selective self-assembled monolayer (SAM) removal Jun 12, 2023 Issued
Array ( [id] => 18866049 [patent_doc_number] => 20230420486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => ATOMIC LAYER DEPOSITION OF HIGH DIELECTRIC CONSTANT MATERIALS [patent_app_type] => utility [patent_app_number] => 18/208710 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/208710
ATOMIC LAYER DEPOSITION OF HIGH DIELECTRIC CONSTANT MATERIALS Jun 11, 2023 Pending
Array ( [id] => 18898591 [patent_doc_number] => 20240014076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SELECTIVE CAPPING OF CONTACT LAYER FOR CMOS DEVICES [patent_app_type] => utility [patent_app_number] => 18/206427 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206427 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206427
Selective capping of contact layer for CMOS devices Jun 5, 2023 Issued
Array ( [id] => 18821060 [patent_doc_number] => 20230395401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => WAFER PROCESSING METHOD AND WAFER PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/324262 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324262 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324262
Wafer processing method and wafer processing system May 25, 2023 Issued
Array ( [id] => 20111499 [patent_doc_number] => 12362235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Barrier free interface between BEOL interconnects [patent_app_type] => utility [patent_app_number] => 18/318917 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 4420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318917
Barrier free interface between BEOL interconnects May 16, 2023 Issued
Array ( [id] => 18631870 [patent_doc_number] => 20230290775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR DEVICE WITH LOW NOISE TRANSISTOR AND LOW TEMPERATURE COEFFICIENT RESISTOR [patent_app_type] => utility [patent_app_number] => 18/317227 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317227 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317227
Semiconductor device with low noise transistor and low temperature coefficient resistor May 14, 2023 Issued
Array ( [id] => 18568700 [patent_doc_number] => 20230259036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => Method for Reducing Line-End Space in Integrated Circuit Patterning [patent_app_type] => utility [patent_app_number] => 18/305536 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305536
Method for reducing line-end space in integrated circuit patterning Apr 23, 2023 Issued
Array ( [id] => 19023063 [patent_doc_number] => 20240079234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => VAPOR DEPOSITION OF TELLURIUM NANOMESH ELECTRONICS ON ARBITRARY SURFACES AT LOW TEMPERATURE [patent_app_type] => utility [patent_app_number] => 18/194098 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194098
Vapor deposition of tellurium nanomesh electronics on arbitrary surfaces at low temperature Mar 30, 2023 Issued
Array ( [id] => 19483971 [patent_doc_number] => 20240332013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/193041 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193041 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193041
Semiconductor structure and manufacturing method thereof Mar 29, 2023 Issued
Array ( [id] => 19483958 [patent_doc_number] => 20240332000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => DOPED SILICON-CONTAINING MATERIALS WITH INCREASED ELECTRICAL, MECHANICAL, AND ETCH CHARACTERISTICS [patent_app_type] => utility [patent_app_number] => 18/192573 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192573 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192573
DOPED SILICON-CONTAINING MATERIALS WITH INCREASED ELECTRICAL, MECHANICAL, AND ETCH CHARACTERISTICS Mar 28, 2023 Pending
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