Search

Rachel L. Zhang

Examiner (ID: 15566, Phone: (571)272-9802 , Office: P/1721 )

Most Active Art Unit
1721
Art Unit(s)
1795, 1709, 1721, 1724
Total Applications
435
Issued Applications
294
Pending Applications
0
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20443154 [patent_doc_number] => 12514000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Semiconductor device structure with fuse and resistor and method for preparing the same [patent_app_type] => utility [patent_app_number] => 18/239859 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 25 [patent_no_of_words] => 5799 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239859
Semiconductor device structure with fuse and resistor and method for preparing the same Aug 29, 2023 Issued
Array ( [id] => 19409122 [patent_doc_number] => 20240292633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/456519 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456519 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/456519
Semiconductor device and method of manufacturing the same Aug 27, 2023 Issued
Array ( [id] => 18835414 [patent_doc_number] => 20230403941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/238520 [patent_app_country] => US [patent_app_date] => 2023-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/238520
Semiconductor device and method for fabricating the same Aug 26, 2023 Issued
Array ( [id] => 19926289 [patent_doc_number] => 12300583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Concealed gate terminal semiconductor packages and related methods [patent_app_type] => utility [patent_app_number] => 18/454970 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 1210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/454970
Concealed gate terminal semiconductor packages and related methods Aug 23, 2023 Issued
Array ( [id] => 18823097 [patent_doc_number] => 20230397438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MAGNETIC MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/452886 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452886 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/452886
Magnetic memory devices Aug 20, 2023 Issued
Array ( [id] => 19806133 [patent_doc_number] => 20250072058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/452584 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/452584
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Aug 20, 2023 Pending
Array ( [id] => 18821195 [patent_doc_number] => 20230395536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 18/451857 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451857
RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE Aug 17, 2023 Pending
Array ( [id] => 19255295 [patent_doc_number] => 20240206292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/450828 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450828 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450828
DISPLAY DEVICE Aug 15, 2023 Pending
Array ( [id] => 20553228 [patent_doc_number] => 12564042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Semiconductor structure and layout structure [patent_app_type] => utility [patent_app_number] => 18/450798 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1219 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450798
Semiconductor structure and layout structure Aug 15, 2023 Issued
Array ( [id] => 18991329 [patent_doc_number] => 20240063298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/234210 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234210
SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF Aug 14, 2023 Pending
Array ( [id] => 19773437 [patent_doc_number] => 20250054863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => FLEXIBLE TRACKPLAN FOR POWER DELIVERY [patent_app_type] => utility [patent_app_number] => 18/448933 [patent_app_country] => US [patent_app_date] => 2023-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448933
FLEXIBLE TRACKPLAN FOR POWER DELIVERY Aug 11, 2023 Pending
Array ( [id] => 19906535 [patent_doc_number] => 12283554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Integrated circuit layout, integrated circuit, and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/447840 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 58 [patent_no_of_words] => 38323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447840
Integrated circuit layout, integrated circuit, and method for fabricating the same Aug 9, 2023 Issued
Array ( [id] => 18975256 [patent_doc_number] => 20240055348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => THREE DIMENSIONAL INTEGRATED CIRCUIT WITH MONOLITHIC INTER-TIER VIAS (MIV) [patent_app_type] => utility [patent_app_number] => 18/447739 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447739
Three dimensional integrated circuit with monolithic inter-tier vias (MIV) Aug 9, 2023 Issued
Array ( [id] => 19925089 [patent_doc_number] => 12299373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Reduced area standard cell abutment configurations [patent_app_type] => utility [patent_app_number] => 18/447187 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 6549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447187
Reduced area standard cell abutment configurations Aug 8, 2023 Issued
Array ( [id] => 19873777 [patent_doc_number] => 12266648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Package structure [patent_app_type] => utility [patent_app_number] => 18/363768 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 11638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363768
Package structure Aug 1, 2023 Issued
Array ( [id] => 19758087 [patent_doc_number] => 20250046652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => FABRICATING DUAL DAMASCENE STRUCTURES USING MULTILAYER PHOTOSENSITIVE DIELECTRICS [patent_app_type] => utility [patent_app_number] => 18/228846 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228846
Fabricating dual damascene structures using multilayer photosensitive dielectrics Jul 31, 2023 Issued
Array ( [id] => 18791191 [patent_doc_number] => 20230380187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MRAM MEMORY CELL LAYOUT FOR MINIMIZING BITCELL AREA [patent_app_type] => utility [patent_app_number] => 18/362817 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362817
MRAM memory cell layout for minimizing bitcell area Jul 30, 2023 Issued
Array ( [id] => 19101048 [patent_doc_number] => 20240120276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING INTER-DIE INTERFACE [patent_app_type] => utility [patent_app_number] => 18/227113 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227113
Three-dimensional semiconductor integrated circuit device including inter-die interface Jul 26, 2023 Issued
Array ( [id] => 18776557 [patent_doc_number] => 20230371399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => UNDER-CUT VIA ELECTRODE FOR SUB 60NM ETCHLESS MRAM DEVICES BY DECOUPLING THE VIA ETCH PROCESS [patent_app_type] => utility [patent_app_number] => 18/360055 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360055 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360055
Under-cut via electrode for sub 60nm etchless MRAM devices by decoupling the via etch process Jul 26, 2023 Issued
Array ( [id] => 18757642 [patent_doc_number] => 20230361105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/355273 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355273 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355273
Integrated circuit device and method Jul 18, 2023 Issued
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