
Rahul Maini
Examiner (ID: 16023, Phone: (571)270-1099 , Office: P/2866 )
| Most Active Art Unit | 2866 |
| Art Unit(s) | 2858, 2866 |
| Total Applications | 480 |
| Issued Applications | 361 |
| Pending Applications | 25 |
| Abandoned Applications | 100 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10400846
[patent_doc_number] => 20150285855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'SYSTEM WITH DUAL FUNCTION LOAD BOARD'
[patent_app_type] => utility
[patent_app_number] => 14/288198
[patent_app_country] => US
[patent_app_date] => 2014-05-27
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Array
(
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[patent_kind] => A1
[patent_issue_date] => 2014-12-25
[patent_title] => 'PRINTED CIRCUIT BOARD, ELECTRONIC APPARATUS AND COMPONENT DETECTION METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/286160
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Array
(
[id] => 10453433
[patent_doc_number] => 20150338448
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[patent_kind] => A1
[patent_issue_date] => 2015-11-26
[patent_title] => 'NOISE DETECTION DEVICE, SYSTEM AND METHOD'
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[patent_app_number] => 14/285604
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Array
(
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[patent_kind] => B2
[patent_issue_date] => 2017-04-18
[patent_title] => 'Work function calibration of a non-contact voltage sensor'
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Array
(
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[patent_issue_date] => 2014-12-04
[patent_title] => 'METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR PACKAGE HAVING A PACKAGE ON PACKAGE (POP) DESIGN'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/284241 | Method and apparatus for testing a semiconductor package having a package on package (PoP) design | May 20, 2014 | Issued |
Array
(
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[patent_title] => 'MEMORY PACKAGE TEST JIG HAVING HARSH CONDITION CREATING STRUCTURE'
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[patent_app_number] => 14/283665
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Array
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[patent_title] => 'Testing of Thru-Silicon Vias'
[patent_app_type] => utility
[patent_app_number] => 14/283116
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/283116 | Testing of thru-silicon vias | May 19, 2014 | Issued |
Array
(
[id] => 12045701
[patent_doc_number] => 09823294
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[patent_kind] => B1
[patent_issue_date] => 2017-11-21
[patent_title] => 'Negative voltage testing methodology and tester'
[patent_app_type] => utility
[patent_app_number] => 14/278957
[patent_app_country] => US
[patent_app_date] => 2014-05-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/278957 | Negative voltage testing methodology and tester | May 14, 2014 | Issued |
Array
(
[id] => 11628682
[patent_doc_number] => 20170138871
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[patent_issue_date] => 2017-05-18
[patent_title] => 'Estimating Subterranean Fluid Viscosity Based on Nuclear Magnetic Resonance (NMR) Data'
[patent_app_type] => utility
[patent_app_number] => 14/429254
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Array
(
[id] => 11326210
[patent_doc_number] => 20160356822
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[patent_issue_date] => 2016-12-08
[patent_title] => 'STRAY MAGNETIC FIELD REJECTION FOR IN-HOLE CURRENT-MEASUREMENT SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 14/913931
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/913931 | Stray magnetic field rejection for in-hole current-measurement systems | Mar 25, 2014 | Issued |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2015-08-20
[patent_title] => 'Method of Manufacturing a Test Socket Body of an Impedance-Matched Test Socket'
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Array
(
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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