
Raj R. Gupta
Examiner (ID: 2557, Phone: (571)270-5707 , Office: P/2829 )
| Most Active Art Unit | 2829 |
| Art Unit(s) | 2814, 2829, 2893 |
| Total Applications | 829 |
| Issued Applications | 593 |
| Pending Applications | 52 |
| Abandoned Applications | 205 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16264862
[patent_doc_number] => 10756310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-25
[patent_title] => Display device
[patent_app_type] => utility
[patent_app_number] => 16/477559
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 7218
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477559
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/477559 | Display device | Sep 28, 2017 | Issued |
Array
(
[id] => 15823239
[patent_doc_number] => 10636816
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Thin film transistor and manufacturing method thereof, array substrate and display panel
[patent_app_type] => utility
[patent_app_number] => 15/766570
[patent_app_country] => US
[patent_app_date] => 2017-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 8301
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15766570
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/766570 | Thin film transistor and manufacturing method thereof, array substrate and display panel | Sep 27, 2017 | Issued |
Array
(
[id] => 14105923
[patent_doc_number] => 20190094637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/767878
[patent_app_country] => US
[patent_app_date] => 2017-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6297
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15767878
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/767878 | Array substrate, display panel and display device | Sep 27, 2017 | Issued |
Array
(
[id] => 15315875
[patent_doc_number] => 10522655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-31
[patent_title] => Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI
[patent_app_type] => utility
[patent_app_number] => 15/711674
[patent_app_country] => US
[patent_app_date] => 2017-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 31
[patent_no_of_words] => 5665
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15711674
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/711674 | Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI | Sep 20, 2017 | Issued |
Array
(
[id] => 15234493
[patent_doc_number] => 10504977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-10
[patent_title] => Organic light-emitting circuit structure having temperature compensation function
[patent_app_type] => utility
[patent_app_number] => 15/707887
[patent_app_country] => US
[patent_app_date] => 2017-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5613
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707887
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/707887 | Organic light-emitting circuit structure having temperature compensation function | Sep 17, 2017 | Issued |
Array
(
[id] => 12061854
[patent_doc_number] => 20170338197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/674406
[patent_app_country] => US
[patent_app_date] => 2017-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 18129
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674406
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/674406 | Semiconductor device and a method of manufacturing the same | Aug 9, 2017 | Issued |
Array
(
[id] => 15475679
[patent_doc_number] => 10553726
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/671199
[patent_app_country] => US
[patent_app_date] => 2017-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 66
[patent_no_of_words] => 25903
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671199
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/671199 | Semiconductor device | Aug 7, 2017 | Issued |
Array
(
[id] => 13695441
[patent_doc_number] => 20170358675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-14
[patent_title] => PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH
[patent_app_type] => utility
[patent_app_number] => 15/668248
[patent_app_country] => US
[patent_app_date] => 2017-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5210
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668248
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/668248 | Precise control of vertical transistor gate length | Aug 2, 2017 | Issued |
Array
(
[id] => 12181851
[patent_doc_number] => 20180040787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-08
[patent_title] => 'Unknown'
[patent_app_type] => utility
[patent_app_number] => 15/663984
[patent_app_country] => US
[patent_app_date] => 2017-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7904
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15663984
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/663984 | Light-emitting component | Jul 30, 2017 | Issued |
Array
(
[id] => 16464237
[patent_doc_number] => 10847600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-24
[patent_title] => Display device and manufacturing method for display device
[patent_app_type] => utility
[patent_app_number] => 16/466360
[patent_app_country] => US
[patent_app_date] => 2017-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 6562
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16466360
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/466360 | Display device and manufacturing method for display device | Jul 27, 2017 | Issued |
Array
(
[id] => 12026845
[patent_doc_number] => 20170316944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-02
[patent_title] => 'SHORT-CHANNEL NFET DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/646570
[patent_app_country] => US
[patent_app_date] => 2017-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5256
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646570
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/646570 | Short-channel NFET device | Jul 10, 2017 | Issued |
Array
(
[id] => 13785601
[patent_doc_number] => 20190006339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => THREE-DIMENSIONAL INTEGRATED FAN-OUT WAFER LEVEL PACKAGE
[patent_app_type] => utility
[patent_app_number] => 15/635329
[patent_app_country] => US
[patent_app_date] => 2017-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3436
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635329
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/635329 | THREE-DIMENSIONAL INTEGRATED FAN-OUT WAFER LEVEL PACKAGE | Jun 27, 2017 | Abandoned |
Array
(
[id] => 11983872
[patent_doc_number] => 20170288027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'METHOD OF FORMING TRENCH SEMICONDUCTOR DEVICE HAVING MULTIPLE TRENCH DEPTHS'
[patent_app_type] => utility
[patent_app_number] => 15/627281
[patent_app_country] => US
[patent_app_date] => 2017-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7146
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627281
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/627281 | Method of forming trench semiconductor device having multiple trench depths | Jun 18, 2017 | Issued |
Array
(
[id] => 12033865
[patent_doc_number] => 20170323964
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'SPLIT FIN FIELD EFFECT TRANSISTOR ENABLING BACK BIAS ON FIN TYPE FIELD EFFECT TRANSISTORS'
[patent_app_type] => utility
[patent_app_number] => 15/592880
[patent_app_country] => US
[patent_app_date] => 2017-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8932
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592880
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/592880 | Split fin field effect transistor enabling back bias on fin type field effect transistors | May 10, 2017 | Issued |
Array
(
[id] => 14024837
[patent_doc_number] => 20190074412
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-07
[patent_title] => MANGANESE-DOPED PHOSPHOR MATERIALS FOR HIGH POWER DENSITY APPLICATIONS
[patent_app_type] => utility
[patent_app_number] => 15/743435
[patent_app_country] => US
[patent_app_date] => 2017-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5507
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15743435
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/743435 | Manganese-doped phosphor materials for high power density applications | May 8, 2017 | Issued |
Array
(
[id] => 11869472
[patent_doc_number] => 20170236757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-17
[patent_title] => 'PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY'
[patent_app_type] => utility
[patent_app_number] => 15/582334
[patent_app_country] => US
[patent_app_date] => 2017-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6392
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15582334
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/582334 | Patterning of vertical nanowire transistor channel and gate with directed self assembly | Apr 27, 2017 | Issued |
Array
(
[id] => 13257253
[patent_doc_number] => 10141324
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-27
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/581576
[patent_app_country] => US
[patent_app_date] => 2017-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 26
[patent_no_of_words] => 15505
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581576
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/581576 | Semiconductor device | Apr 27, 2017 | Issued |
Array
(
[id] => 14021673
[patent_doc_number] => 20190072830
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-07
[patent_title] => Method of Manufacturing Pixel Structure
[patent_app_type] => utility
[patent_app_number] => 15/567264
[patent_app_country] => US
[patent_app_date] => 2017-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6350
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15567264
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/567264 | Method of Manufacturing Pixel Structure | Apr 26, 2017 | Abandoned |
Array
(
[id] => 12162732
[patent_doc_number] => 20180033998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-01
[patent_title] => 'Organic Light Emitting Diode Display'
[patent_app_type] => utility
[patent_app_number] => 15/499759
[patent_app_country] => US
[patent_app_date] => 2017-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7651
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499759
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/499759 | Organic light emitting diode display | Apr 26, 2017 | Issued |
Array
(
[id] => 12033869
[patent_doc_number] => 20170323968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH'
[patent_app_type] => utility
[patent_app_number] => 15/496797
[patent_app_country] => US
[patent_app_date] => 2017-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5302
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496797
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/496797 | Precise control of vertical transistor gate length | Apr 24, 2017 | Issued |