
Raj R. Gupta
Examiner (ID: 12575)
| Most Active Art Unit | 2829 |
| Art Unit(s) | 2829, 2893, 2814 |
| Total Applications | 829 |
| Issued Applications | 593 |
| Pending Applications | 52 |
| Abandoned Applications | 205 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4333327
[patent_doc_number] => 06317821
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Virtual single-cycle execution in pipelined processors'
[patent_app_type] => 1
[patent_app_number] => 9/080787
[patent_app_country] => US
[patent_app_date] => 1998-05-18
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[pdf_file] => patents/06/317/06317821.pdf
[firstpage_image] =>[orig_patent_app_number] => 080787
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/080787 | Virtual single-cycle execution in pipelined processors | May 17, 1998 | Issued |
Array
(
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[patent_doc_number] => 06205545
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[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance'
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[patent_app_date] => 1998-04-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070585 | Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance | Apr 29, 1998 | Issued |
Array
(
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[patent_issue_date] => 2000-08-15
[patent_title] => 'Method and apparatus for dispatching instructions to execution units in waves'
[patent_app_type] => 1
[patent_app_number] => 9/070076
[patent_app_country] => US
[patent_app_date] => 1998-04-30
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[patent_drawing_sheets_cnt] => 8
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070076 | Method and apparatus for dispatching instructions to execution units in waves | Apr 29, 1998 | Issued |
Array
(
[id] => 4162577
[patent_doc_number] => 06032248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Microcontroller including a single memory module having a data memory sector and a code memory sector and supporting simultaneous read/write access to both sectors'
[patent_app_type] => 1
[patent_app_number] => 9/069884
[patent_app_country] => US
[patent_app_date] => 1998-04-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/069884 | Microcontroller including a single memory module having a data memory sector and a code memory sector and supporting simultaneous read/write access to both sectors | Apr 28, 1998 | Issued |
Array
(
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[patent_doc_number] => 05961638
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[patent_issue_date] => 1999-10-05
[patent_title] => 'Branch prediction mechanism employing branch selectors to select a branch prediction'
[patent_app_type] => 1
[patent_app_number] => 9/067990
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[patent_app_date] => 1998-04-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/067990 | Branch prediction mechanism employing branch selectors to select a branch prediction | Apr 28, 1998 | Issued |
Array
(
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[patent_title] => 'Computer program product and method for efficiently selecting one action from among alternative actions'
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[patent_app_number] => 9/069006
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[firstpage_image] =>[orig_patent_app_number] => 069006
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/069006 | Computer program product and method for efficiently selecting one action from among alternative actions | Apr 27, 1998 | Issued |
Array
(
[id] => 4121213
[patent_doc_number] => 06023737
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[patent_title] => 'Multi-stage pipelined data coalescing for improved frequency operation'
[patent_app_type] => 1
[patent_app_number] => 9/066014
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/066014 | Multi-stage pipelined data coalescing for improved frequency operation | Apr 23, 1998 | Issued |
Array
(
[id] => 4371260
[patent_doc_number] => 06216215
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'Method and apparatus for senior loads'
[patent_app_type] => 1
[patent_app_number] => 9/053932
[patent_app_country] => US
[patent_app_date] => 1998-04-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/216/06216215.pdf
[firstpage_image] =>[orig_patent_app_number] => 053932
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/053932 | Method and apparatus for senior loads | Apr 1, 1998 | Issued |
Array
(
[id] => 4178017
[patent_doc_number] => 06108773
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[patent_issue_date] => 2000-08-22
[patent_title] => 'Apparatus and method for branch target address calculation during instruction decode'
[patent_app_type] => 1
[patent_app_number] => 9/052624
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/052624 | Apparatus and method for branch target address calculation during instruction decode | Mar 30, 1998 | Issued |
Array
(
[id] => 4195248
[patent_doc_number] => 06085312
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[patent_issue_date] => 2000-07-04
[patent_title] => 'Method and apparatus for handling imprecise exceptions'
[patent_app_type] => 1
[patent_app_number] => 9/052994
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[firstpage_image] =>[orig_patent_app_number] => 052994
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Array
(
[id] => 7613831
[patent_doc_number] => 06898700
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[patent_title] => 'Efficient saving and restoring state in task switching'
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Array
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Array
(
[id] => 1495397
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[patent_title] => 'Apparatus and method for performing intra-add operation'
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Array
(
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Array
(
[id] => 4192759
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Array
(
[id] => 4114621
[patent_doc_number] => 06049860
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[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Pipelined floating point stores'
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[pdf_file] => patents/06/049/06049860.pdf
[firstpage_image] =>[orig_patent_app_number] => 025939
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/025939 | Pipelined floating point stores | Feb 18, 1998 | Issued |
| 09/120275 | FAST EMPTY STATE INSTRUCTION FOR A MICROPROCESSOR INCLUDING MULTIPLE REGISTER FILES MAPPED TO THE SAME LOGICAL STORAGE | Feb 12, 1998 | Abandoned |
Array
(
[id] => 4022455
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Array
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Array
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